JPS6020224A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make an operation control possible when necessary by providing a gate function in the output part of the system clock generation circuit, and at the same time selectively controlling the sending of the signals inputted from the internal as well as the external terminals. CONSTITUTION:An outside-fitted crystal oscillator is installed in external terminals P2 and P3, and a basic clock phi is formed by reversely amplifying 6 and dividing 7 its output. The clock phi is inputted as clock phi1 in the clock terminal of FF's 1 and 2, NOR gate G1 as well as the timer. A signal A is inputted in FF 1 from the external terminal P1, and the output Q becomes a control signal for NOR gate-G1. The clock, which passed through a gate-G1, is transmitted to the internal circuit as a system clock phi2 through the inverter IV, and also inputted into an NOR gate G2. The clock stop instruction B is inputted into an input terminal D of FF2 from CPU; the clock starting instruction C is inputted into a terminal R; the output Q controls the NOR gate G2, and outputs the system clock phi3, then controlling the operation by the external signal A, the internal signals B and C.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device, and is a technology that is effective for, for example, a l-chip microcomputer configured with CMOS (complementary MOS). be.

[Background technology]

The present inventor has developed a system in a semiconductor integrated circuit device, such as a one-chip microcomputer, by making it possible to access the system from both the inside (software) and the outside (control terminal). We considered reducing power consumption by temporarily stopping the system clock when no processing is being performed or when accessing low-speed memory.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device including a microprocessor that achieves low power consumption.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a gate function is provided at the output section of the system clock generation circuit, and its output is selectively controlled by an internal signal and a signal input from an external terminal.

〔Example〕

FIG. 1 shows a block diagram of an embodiment in which the present invention is applied to a one-chip microcomputer. In the figure, each circuit block surrounded by a broken line is formed on a semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique. Although not particularly limited, each of the circuit blocks described above is constituted by an 0M03 circuit.

The symbol 1 indicates the microprocessor CPU
It is. The main constituent blocks of this microprocessor CPU are illustrated as a representative example. That is, the microprocessor cPU includes an accumulator A, an index register X, a condition code register cc, a stack pointer SP, and a program counter PC.
H, PCL and arithmetic logic unit) ALU and cp
It is composed of the U controller CPUCONT, etc. Since the configuration of such a microprocessor CPU is well known, detailed explanation thereof will be omitted. .

The symbols 2 to 5 are input and output ports, and the symbols 2 to 4 are the input and output ports.
A data direction register RA or RC is provided,
Used as an input/output boat. Further, the symbol 5 indicates an input-only port.

What is indicated by the symbol 6 is an amplifier circuit for configuring an oscillation circuit, and although not particularly limited, oscillation is performed by connecting an external crystal resonator or the like. This oscillation output is input to a frequency dividing circuit 7, which forms a lock signal necessary for the operation of the microprocessor CPU, and sends it out through a gate circuit 8. The gate circuit 8 receives a control signal supplied from an external terminal,
The gate control operation is performed by an internally generated control signal.

A RAM (Random Access Memory) is indicated by the symbol 9 and is mainly used as a temporary data storage circuit. Also, what is indicated by the symbol 1° is a ROM (read-only memory) in which programs for various information processing are written.

The above circuit blocks are connected to each other by a bus BUS with the microprocessor CPU as the center. This bus BUS includes an address bus and a data bus.

FIG. 2 shows a circuit diagram of one embodiment of a circuit that forms the system clock.

The output and input of the inverting amplifier circuit 6 are respectively connected to an external terminal P.
2. Connected to P3. Also, between the input and output,
A bias resistor R is provided. These external terminals P2.
This oscillation signal, which performs oscillation by connecting a crystal resonator or the like to P3, is transmitted to the frequency dividing circuit 7. The clock signal φ generated by the frequency dividing circuit 7 is inputted to a NOR gate (Gl) constituting a gate circuit 8 on the one hand.

Further, the clock signal φ is supplied to the clock terminal C of the flip-flops FFI and FF2 on the other side.

It is also supplied as the clock φl of a circuit that requires a constant clock, such as a timer circuit.

A signal A from an external terminal P1 is supplied to the input terminal of the flip-flop FFI. The output signal Q of this flip-flop FFI is N as shown below.

It is used as a control signal for the R gate circuit G1.

The clock passed through the NOR gate path G1 is not particularly limited, but on the one hand, the inverter! ■Inside as the first system clock through! transmitted to the circuit. Also, on the other hand, it is input to the NOR gate circuit G2.

A signal formed by an internal circuit such as a microprocessor CPU, in other words, a signal formed by a specific command signal (clock stop command) B is input to the input terminal of the flip-flop FF2. Further, the reset terminal R is supplied with a clock activation signal C, which is similarly generated by the internal circuit. This clock activation signal is generated based on a timer circuit, an interrupt signal, or the like since most of the internal circuits have stopped their operations. The output signal Q of this flip-flop FF2 is the NOR
It is used as a control signal for gate circuit G2. This NO
A second system clock φ3 is supplied from the R gate circuit G2 to the internal circuit.

Next, the operation of the embodiment circuit shown in FIG. 2 will be explained.

When flip controllers 1FFI and FF2 are both in the reset state, their respective output signals Q are both low level (
Since the logic is "0"), the NOR gate circuit Gl
, G2 both have their gates open. therefore,
1st. Second system clock φ2. Both φ3 are supplied to the internal circuit. In this state, when the external terminal P1 is set to a high level, the output signal Q of the flip-flop FFI becomes high level in synchronization with the clock φ. As a result, the NOR gate circuit G1 is closed, so that the system clock φ2. The transmission of φ3 is stopped.

In this way, the system clocks φ1, φ are input from the external terminal P1.
When the transmission of the clock signal φ2 is stopped, the system clock φ
1. Sending of φ2 is started again.

Further, when the stop signal B is set to high level by executing the above-mentioned specific instruction formed by internal software, the output signal Q of the flip-flop FF2 is changed to the clock φ
is set to high level in synchronization with As a result, the NOR gate circuit G2 is closed, so that the transmission of the system clock φ3 is stopped. That is, in this state, the system clock φ2 is sent out and the sending of the system clock φ3 is stopped.

Note that by constantly sending out the clock φ1,
Circuits that need to be in constant operation, such as timer circuits, are in operation. Therefore, the system clock activation signal C is generated by the circuit that is activated by the system clock φ2 or φ1. For example, the activation signal C is generated by a timer circuit or an interrupt circuit that measures a certain amount of time. As a result, flip-flop FF2 is reset. Therefore, since the NOR gate circuit G2 is opened by the low level of the output signal Q, the system clock signal .nu..phi.3 is sent out again.

In this embodiment, the system clock is transmitted in this way,
Stopping can be controlled by both signals supplied from external terminals and signals generated by internal circuitry (software).

(Effects) (1) By being able to control the sending and stopping of the system clock from the outside directly or by internal circuitry (software), it is possible to achieve the effect that operation control can be performed as necessary. For example, when exchanging data with a low-speed memory, it is possible to keep only the necessary portions in operation and stop the operations of other circuit blocks. Alternatively, when no information processing is performed, the operation of all circuit blocks can be stopped. By providing such a function, especially in the 0M03 circuit, power consumption can be significantly reduced because DC current is consumed only when a signal changes. In addition, in a static type circuit where the logic circuit consists of a load means and a driving means, power consumption increases in proportion to its operating frequency, so this also applies to so-called E/E type MO3 and E/D type MOS circuits. Lower power consumption can be achieved.

(2) Sending and stopping of the system clock can be controlled both directly from an external terminal or by software. This has the effect of making the control more flexible.

(3) With (11 and (2)) above, it is possible to expand the usage or application of semiconductor integrated circuit devices such as microcomputers.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, a high-frequency clock and a low-frequency clock may be prepared as the system clock, and the gate circuit may switch between them and send them out. Furthermore, the system configuration of the microcomputer can be modified in various ways.

[Application field]

In the above explanation, the invention made by the present inventor has mainly been explained using a one-chip microcomputer as an example, which is the technical field behind the invention. It can be widely used in digital semiconductor integrated circuit devices that perform

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention applied to a microcomputer, and FIG. 2 is a circuit diagram showing an embodiment of a circuit forming the system clock. 1...Microprocessor CPU, 2-5...Boat,
6... Inverting amplifier circuit, 7... Frequency dividing circuit, 8... Gate circuit, 9... RAM, 10... -RO1

Claims (1)

[Claims] 1. A reference oscillation circuit, a frequency dividing circuit that receives the oscillation output and forms a predetermined clock signal, and a control signal from an external terminal or a signal formed by an internal circuit to generate the clock signal. 1. A semiconductor integrated circuit device comprising a gate and a circuit for selectively transmitting signals, and a microprocessor that operates in response to a clock signal passed through the gate circuit. 2. The semiconductor integrated circuit device according to claim 1, wherein the signal formed by the internal circuit is formed by a specific command word or a timer. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the semiconductor integrated circuit device is a one-chip microcomputer configured with 0M03 circuits.