JPH02207312A - Clock generating circuit - Google Patents

Abstract

PURPOSE:To sufficiently draw out the performance of a circuit by switching a clock signal supplied to a microprocessor according to the change of an environmental temperature, and driving the microprocessor by means of the optimal clock signal. CONSTITUTION:A thermister 1 generates a thermister output voltage 101 corresponding to the environmental temperature, a voltage comparing circuit 2 compares the voltage 101 with a reference voltage, when the voltage 101 is larger, a clock selective A signal 102 at a logic '1' is outputted. A clock A generating circuit 3 outputs a clock A signal 103, and a clock B generating circuit 4 generates a clock B signal 104 having a higher frequency than that of the clock A signal 103. A clock switching circuit 5 selects the clock A signal 103 when the signal 102 is at the logic '1', the circuit 5 selects the clock B signal 104 when the signal 102 is not at the logic '1', and outputs the signal to a microprocessor 6. Thus the maximal speed performance of the microprocessor allowable in the environmental temperature is drawn out.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to microprocessor application circuits, and more particularly to clock generation circuits.

[Conventional technology]

Conventional clock generation circuits have been configured to generate a single frequency clock.

[Problem to be solved by the invention]

A microprocessor configured with an MO8 integrated circuit is generally capable of faster operation in a low temperature environment than in a high temperature environment.

On the other hand, in conventional circuits, a single frequency reference clock is used as input to the microprocessor.
Furthermore, the frequency needed to be within a range that would guarantee stable operation of the microprocessor in a high-temperature environment.

Therefore, even though microprocessors are capable of faster operation in low-temperature environments, they have not been able to bring out their full potential.

[Means to solve the problem]

The clock generation circuit of the present invention includes a clock A generation circuit that generates a clock A signal, a clock B generation circuit that generates a clock B signal having a higher frequency than the clock A signal, a thermistor that measures environmental temperature, and a thermistor. Compare the output voltage and internal reference voltage with hysteresis added,
A voltage comparator circuit that outputs a clock selection A signal that is logic "1" when the output voltage of the thermistor is higher and logic "0" otherwise, the clock selection A signal, the quack selection B signal described later, and the clock A signal. and the clock B signal, and if at least one of the clock selection A signal and the clock selection B signal is logic "1", the clock A signal is selected, and if not, the clock B signal is selected as the selected clock signal. and a clock switching circuit that performs a glitch-free switching operation at the time of clock switching.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Thermistor l generates a thermistor output voltage 101 depending on the ambient temperature. The voltage comparator circuit 2 compares the thermistor output voltage 101 and a reference voltage generated inside the voltage comparator circuit with hysteresis added, and if the thermistor output voltage is larger, the logic is "1", otherwise, the logic is "1".
0'', it outputs the clock selection A signal 102.The clock A generation circuit 3 outputs the clock A signal 103.The clock B generation circuit 4 outputs the clock B signal having a higher frequency than the clock A signal. The clock switching circuit 5 receives the clock A signal 103 and the clock B signal 104, and switches the clock when at least one of the clock selection A signal 102 and the clock selection B signal 107 is logic "1". If not, the clock B signal 104 is selected and outputted to the microprocessor 6 as a select signal 105.
and is used as the reference clock for the microprocessor. A register 7 connected to the address/data bus of the microprocessor functions as an I10 port of the microprocessor 6, and sets the clock selection B signal to logic "1" or logic "0" according to instructions from the microprocessor 6.

FIG. 2 shows an embodiment of the voltage comparator circuit 2. In FIG.

Thermistor output voltage 101 is input to operational amplifier 201 through resistor 202. The reference voltage to be compared with the thermistor output voltage is connected between Vcc and GND through a resistor 202,
203. By applying the output voltage of the operational amplifier 201 between the resistors 203 and 204, hysteresis can be added to the thermistor output voltage 101.

FIG. 3 shows an embodiment of the clock switching circuit 5. In FIG. 1, when one of the clock A signal and clock B signal is selected, the clock selection A signal and the clock B signal are selected.
If the other clock signal is selected due to a change in the clock selection B signal, glitches may occur on the selected signal during the transient state. This phenomenon occurs because the two types of clock signals are asynchronous, but by configuring the clock switching circuit 5 as shown in FIG. 3, the occurrence of glitches can be prevented. The Iffy A signal 103 is input to the inverter 50 and the AND gate 58.

Clock B signal 104 is input to inverter 51 and AND gate 59. The output 501 of the inverter 50 is input to the clock input of the D flip-flop 56. Further, the output 502 of the inverter 51 is input to the clock input of the D flip-flop 57. Clock selection A signal 102 and clock selection B signal 107 are input to OR gate 52 . The output 503 of the OR gate 52 is AN
It is input to the D gate 54 and the inverter 53. Output 504 of inverter 53 is input to AND gate 55 . The output 505 of AND gate 54 is input to the data input of D flip-flop 56, and the output 506 of AND gate 55 is input to the data input of D flip-flop 57. The positive output 507 of the D flip-flop 56 is AN
The negative output 508 of the D gate 58 is input to the AND gate 55 . Also, the positive output 509 of the D flip-flop 57
is applied to the AND gate 59, and the negative output 510 is applied to the AND gate 5.
4 is input. Output 511 of AND gate 58 and A
Output 512 of ND gate 59 is input to OR gate 60 . The output of OR gate 60 is selected clock signal 10
5 to the microprocessor.

FIG. 4 is a timing chart illustrating the operations of FIGS. 2 and 3. Thermistor output voltage 1 at point (a)
01 exceeds the reference voltage α, the clock selection signal 102, which is the output of the voltage comparator circuit 2, changes from logic "0" to "1n".As a result, the output 506 of the AND gate 55 changes to "0", and the clock At the falling edge of the B signal 104, the output of the D flip-flop 57 is inverted.As a result, the input 509 of the AND gate 59 becomes logic "0".
Clock B signal 104, which is the other input of AND gate 59, is no longer transmitted to the next stage. Due to the inversion of the output of the D flip-flop 57, both inputs of the AND gate 540 become logic "1", so the output signal 505 changes from "0" to "
1", and the output of the D flip-flop 56 is inverted at the fall of the 0tsuk A signal 103. Therefore,
The input signal 507 of the AND gate 58 becomes a logic "1", and the clock A signal 103, which is the other input of the AND gate 58, is outputted to the microprocessor as the select disturb signal 105 through the OR gate 60. Ru.

When the thermistor output voltage 101 exceeds the reference voltage β at point (b), the clock selection signal 102, which is the output of the voltage comparison circuit 2, changes from logic "1" to "0". As a result, the output 505 of the AND gate 54 changes to "0", and the output of the D flip-flop 56 is inverted at the falling edge of the clock A signal 103. As a result, the input 507 of the AND gate 58 becomes logic "0", so the clock A signal 103, which is the other input of the AND gate 58, is no longer transmitted to the next stage. Due to the inversion of the outputs of D-Furi, Pflo, and Pf 56, both inputs of AND gate 550 become logic "1", so the output signal 506 changes from "0" to "1", and at the falling edge of clock B signal 104. The output of the D flip-flop 57 is inverted.For this reason, the input signal 509 of the AND gate 59 becomes logic "1", and the clock B signal 104, which is the other input of the AND gate 59, is inverted through the OR gate 60. The selected clock signal 105 is outputted to the microprocessor.

Further, in this embodiment, as shown in FIG. 1, the clock can be selected by the clock selection B signal 107 outputted from the register 7 functioning as the I10 port of the microprocessor 6. In Figure 4, (C)
When the clock selection B signal changes from logic "0" to "1" at the point, the output 506 of the AND gate 55 changes to "0", and the output of the D flip-flop 57 is inverted at the falling edge of the clock B signal 104. do. , this causes the input 509 of the AND gate 59 to become logic "0", so the clock B signal 104, which is the other input of the AND gate 59,
is not transmitted to the next stage. D flip flop 57
Due to the inversion of the output of the AND gate 54, the logic “
1", the output signal 505 changes from "0" to "1" and becomes black.

When the A signal 103 falls, the D flip-flop 5
The output of 6 is inverted. Therefore, the AND gate 580 input signal 507 becomes logic "1", and the clock A signal 103, which is the other input of the AND gate 58, becomes O.
The selection clock signal 105 is output to the microprocessor via the R gate 60.

By configuring in this manner, it becomes possible to switch the output signal not only in response to temperature changes but also in response to various external and internal factors. In other words, temperature changes in peripheral devices,
The clock can be switched and used based on the microprocessor's judgment as to whether to use a device for which slow or slow processing is more advantageous.

As explained above, this embodiment uses a clock generation circuit, a clock A generation circuit that generates a clock A signal, a clock B generation circuit that generates a clock B signal having a higher frequency than the clock eight signals, and a clock B generation circuit that measures the environmental temperature. Compares the thermistor's output voltage and internal reference voltage with hysteresis added, and outputs a clock selection A signal that becomes logic "1" if the thermistor's output voltage is higher, and logic "0" otherwise. a voltage comparator circuit, a clock selection A signal, a clock selection B signal described later, and a clock A
Input the signal and the clock B signal, and if at least one of the clock selection A signal and the clock selection B signal is logic "1", select the A signal, otherwise select the clock B signal and select the clock. output as a signal,
and a clock switching circuit that performs a glitch-free switching operation when switching clocks, and a microprocessor that inputs a selected clock signal as a reference clock signal.
By configuring a register that is connected to a microprocessor via an address/data bus and that outputs a clock selection B signal, the microprocessor can be This makes it possible to bring out the maximum speed performance of the processor, and also allows the microprocessor itself to select its operating speed.

〔Effect of the invention〕

As explained above, the present invention can switch the lock signal supplied to the microprocessor in response to changes in environmental temperature, drive the microprocessor with an optimal lock signal, and fully bring out its performance. Become.

The detailed circuit diagram of the clock switching circuit shown in FIG. 1 is a timing chart showing the operation of the second part.

1... Thermistor, 2... Voltage comparison circuit, 3... Clock A generation circuit, 4...
・Clock B generation circuit, 5... Clock switching circuit, 6... Microprocessor, 7...
...Register, 101...Thermistor output voltage, 102...Clock selection A signal, 103...
...Clock A signal, 104...Clock B signal, 105...Selected clock signal, 10
6...Address/data bus, 107...
... Clock selection B signal, 201 ... Humperator, 202.203, 204 ... Resistor, 5
0゜51.53・・・Inverter, 52.60・
...OR gate, 54, 55, 58.59...
...AND game), 56.57...D flip-flop.

Claims (1)

[Claims] A temperature detection means for detecting the ambient environment temperature, a clock generation circuit for outputting a clock signal of a plurality of cycles, and a microprocessor that performs processing in response to the clock signal. 1. A clock generation circuit comprising: a clock switching circuit that selects one of the periodic clock signals and supplies the selected clock signal to the microprocessor.