JPH0786890A - External edge detecting circuit for microcomputer - Google Patents

Abstract

PURPOSE:To prevent the malfunctions of an external edge detecting circuit by using a reset circuit which eliminates an edge detecting signal that is produced by the change of the input signal produced when a port function display signal changes. CONSTITUTION:An external edge detecting circuit contains a reset circuit 30 which supplies an input signal DIN received from a port part and a port function display signal F that changes by the input/output changeover of the port part and detects the change of the signal DIN due to the change of the signal F to produce a reset signal S37. Then an edge detecting circuit is added to input the signal DIN and output it synchronously with a clock signal CLK and to be reset by the signal S37. When both signals DIN and F are supplied to a detecting means, the change of the signal DIN due to the change of the signal F is detected and the signal S37 is produced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external edge detecting circuit used in a microcomputer or the like.

[0002]

2. Description of the Related Art FIG. 2 is a schematic block diagram showing a configuration example of a conventional microcomputer (hereinafter referred to as a microcomputer). This microcomputer is a central processing unit (Central Proc) that performs arithmetic processing according to a program.
essing Unit (hereinafter referred to as CPU) 1, a program memory 2 for storing a program, a data memory 3 for writing and reading data from the CPU, a plurality of external terminals 4-1 to 4-4 connected to peripheral devices, 1 for use in exchanging data between the microcomputer and the outside
A plurality of port units 5-1 to 5-4 having a secondary function and a secondary function to be used as a certain special function, a signal DIN input from the outside is detected, and a detection signal EG is supplied to each block inside the microcomputer. A plurality of external edge detection circuits 6 and an interrupt control block 7 which outputs an interrupt request signal INT so that when there are interrupt requests from a plurality of ports, the interrupts are prioritized and interrupts are executed from the one having the highest urgency. I have it. FIG. 3 is a schematic block diagram showing a configuration example of the port units 5-1 to 5-4 in FIG. The port unit 5-1 includes an output buffer 11, an input buffer 12, and a port mode control register 15. The output buffer 11 has an input side connected to each block inside the microcomputer via an input terminal 13, and an output side connected to an external terminal 4-1. The input side of the input buffer 12 is connected to the external terminal 4-1 and the output side is connected to the external edge detection circuit 6 via the output terminal 14, and outputs the input signal DIN. The output sections of the output buffer 11 and the input buffer 12 are based on the control signal C from the microcomputer, and the port mode control register 15
It has a tri-state configuration that is controlled via. The same applies to the port units 5-2 to 5-4.

FIG. 4 is a circuit diagram showing a configuration example of the external edge detection circuit 6 shown in FIG. The external edge detection circuit 6 is a delay flip-flop (hereinafter referred to as D-FF).
21, D-FF 22, and 2-input AND gates 23 and 2
4 and. The D-FF 21 receives the input signal DI
It is a circuit that inputs N and outputs it in synchronization with the falling edge of the clock signal CLK. The D-FF 22 is the D-FF 21.
Is a circuit which inputs the output signal of and outputs it in synchronization with the fall of the clock signal CLK. 2-input AND gate 2
Reference numeral 3 is a circuit that outputs a logical product of the inverted output signal of the D-FF 21 and the output signal of the D-FF 22. 2-input AND
The gate 24 outputs the output signal of the D-FF 21 and the D-FF 22.
Is a circuit that outputs a logical product with the inverted output signal of. Figure 5
4 is a time chart for explaining the operation of FIG. 2, FIG. 3, and FIG. 4, in which the horizontal axis represents time and the vertical axis represents voltage. The operation of FIGS. 2, 3 and 4 will be described with reference to this figure. The primary function F1 is defined as a function used for exchanging data between the microcomputer and the outside, and the secondary function F2 is defined as a function used as an input-only port to the external edge detection circuit 6. The input signal DIN is supplied to the port section 5-
1 is a signal output from the terminal 1, and when the port unit 5-1 is set to the primary function F1, it is at a high level (hereinafter,
It is fixed to "H") so that the external edge detection circuit 6 does not operate. Port part 5-1 is 2
When the next function F2 is set, the input signal DIN becomes the level of the data applied to the external terminal 4-1 at that time. Here, when the input signal DIN changes from "H" to a low level (hereinafter referred to as "L"), the inverted output Q2 of the D-FF 21 changes from "L" to "H" at the next fall of the clock signal CLK. Change and its inverted output Q2 and DF
AND gate 2 that outputs a logical product with the output Q1 of F22
A falling edge detection signal EG1 is output from 3.
Similarly, when the input signal DIN changes from “L” to “H”, the output Q1 of the D-FF 21 outputs the next clock signal CLK.
Changes from "L" to "H" at the falling edge of the output Q
1 and the inverted output Q2 of the D-FF 22 are output from the AND gate 24 which outputs a rising edge detection signal EG2.
Is output.

[0004]

However, the external edge detection circuit of FIG. 4 used in the conventional microcomputer or the like has the following problems. In the conventional circuits shown in FIG. 2, FIG. 3, and FIG. 4, when the port section 5-1 is set to the primary function F1, the input signal DIN is fixed at "H", but the external terminal 4 When the level of the data applied to -1 is "L", the input signal DIN changes from "H" to "L" when the port section 5-1 is set to the secondary function F2. Therefore, the falling edge is detected. That is, the external edge detection circuit 6 outputs the edge detection signal even though no edge has occurred at the external terminal 4-1. SUMMARY OF THE INVENTION The present invention solves the problem that the above-described conventional technique has a malfunction that the external edge detection circuit outputs an edge detection signal even though no edge is generated in the external terminal. A reset circuit for resetting is provided to provide an external edge detection circuit that prevents malfunction.

[0005]

In order to solve the above-mentioned problems, a first aspect of the present invention is provided with a port unit whose input / output function is switched, and a signal synchronized with a clock signal is input / output to / from the port unit. In an external edge detection circuit of a microcomputer, which is provided in a microcomputer, detects an edge of a signal from a port unit in synchronization with the clock signal, and has an edge detection unit that causes the microcomputer to perform signal processing according to the detection result, The following measures are taken. That is, an input signal from the port unit and a port function display signal that changes when inputting / outputting the port unit is input, a change in the input signal caused by a change in the port function display signal is detected, and a reset signal is detected. And a synchronization means for outputting the reset signal in synchronization with the clock signal to reset the edge detection unit. Second
In the invention, the detecting means is composed of an AND circuit, and the synchronizing means is composed of a flip-flop.

[0006]

According to the first and second aspects of the present invention, since the external edge detection circuit is configured as described above, the detection means displays an input signal from the port section and a port function display that changes when the input / output of the port section is switched. When a signal is input, a change in the input signal due to a change in the port function display signal is detected and a reset signal is generated. Therefore, the edge detection unit is reset before generating the edge detection signal. Therefore, the above problem can be solved.

[0007]

FIG. 1 is a circuit diagram of an external edge detection circuit showing an embodiment of the present invention. The external edge detection circuit corresponds to the external edge detection circuit 6 of the microcomputer shown in FIG. This external edge detection circuit is provided with the port section 5-1.
Input signal DIN and a port function display signal F which changes when the input / output of the port unit 5-1 is switched, and the input signal DI caused by the change of the port function display signal F is input.
A reset unit 30 that detects a change in N and generates a reset signal S37, and an edge detection that receives the input signal DIN, outputs the signal in synchronization with the clock signal CLK, and is reset by the output signal S37 of the reset unit. Section is provided. The reset unit 30 has inverters 31 and 32 that invert the port function display signal F. Inverter 3
The output side of 2 is connected to one input side of the 2-input NOR gate 33, and the reset signal RST is input to the other input side. The output side of the 2-input NOR gate 33 is connected to a set input terminal S of an RS (reset / set) flip-flop (hereinafter referred to as RS-FF) 34. RS-
The FF 34 has 2-input NOR gates 34a and 34b. The two-input NOR gates 34a and 34b are connected between the set input terminal S and the reset input terminal R and the output terminal Q in a crossed manner.

The input signal DIN, the output of the inverter 31,
And the output of the RS-FF 34 is a 3-input NOR gate 35.
Are connected to the input side of each. The output side of the 3-input NOR gate 35 is connected to one input side of the 2-input AND gate 36. The output side of the 2-input AND gate 36 is connected to the input terminal D of the D-FF 37. D
The -FF 37 is composed of a positive edge trigger D-FF. The clock signal CLK is input to the clock input terminal CK. The inverting output terminal Q2 of the D-FF 37 has 2 inputs A
It is connected to the other input side of the ND gate 36. D-
The reset signal S37 is output from the output terminal Q1 of the FF37. The reset signal RST is input to the reset input terminal R of the D-FF 37. Output Q1 of D-FF37 is R
It is connected to the reset input terminal R of the S-FF 34 and also to the reset input terminal R of the D-FFs 41 and 42. D-FF 41 and 42 are negative edge triggers D-
It is composed of FF. The clock signal CLK is input to the clock input terminal CK. Inverted output Q of D-FF41
2 is connected to one input side of the 2-input AND gate 43, and the output Q1 of the D-FF 42 is the 2-input AND gate 43.
Is connected to the other input side of. From the output side of the 2-input AND gate 43, the falling edge detection signal EG1
1 is output. The output Q1 of the D-FF41 is a 2-input AND
It is connected to one input side of the gate 44 and
It is connected to the input terminal D of F42. The inverted output Q2 of the D-FF 42 is connected to the other input side of the 2-input AND gate 44. The rising edge detection signal EG12 is output from the output side of the 2-input AND gate 44.

FIG. 6 is a time chart for explaining the operation of FIG. 1, in which the horizontal axis represents time and the vertical axis represents voltage. The operation of FIG. 1 will be described with reference to this figure. In the initial state, the reset signal RST causes the output Q of the RS-FF 34 to be "L", and the reset signal S37 which is the output of the D-FF 37 also be "L". Port part has primary function F
Since it is 1, the port function display signal F is "L" and the input signal DIN is fixed to "H". Therefore, the output Q1 and D-F of D-FF41
The output Q1 of F42 is always "H". Next, when the port section becomes the secondary function F2, the port function display signal F
Becomes "H". At this time, it is assumed that "L" is applied to the external terminal. Then, the input signal DIN changes to "L". When the input signal DIN changes to "L", the output side of the 2-input AND gate 36 becomes "H". The reset signal S37 becomes "H" by the D-FF 37 taking in this "H" at the rising edge of the clock signal CLK. Therefore, the D-FFs 41 and 42 are reset. That is, since the outputs of the D-FFs 41 and 42 are reset before they change at the next falling edge of the clock signal CLK, the falling edge detection signal EG11 is not output. Further, when the reset signal S37 becomes "H", the output side of the 2-input AND gate 36 becomes "L", so that the reset signal S37 becomes "L" at the next rising of the clock signal CLK, and the D-FF 41, Reset of 42 is prohibited. When the reset signal S37 becomes "H", RS
Since the -FF 34 is also reset and the output Q of the RS-FF 34 becomes "H", the reset signal S37 becomes "L" and does not change. That is, the reset signal S37 becomes "H" only when the port function display signal F becomes "H" and the input signal DIN changes to "L".

As described above, in the present embodiment, in the external edge detection circuit, the edge detection signal is generated by the change of the input signal DIN generated when the port section is switched from the primary function F1 to the secondary function F2. A reset circuit is provided to prevent this. Therefore, malfunction of the external edge detection circuit can be prevented. The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (A) The entire configuration of the microcomputer shown in FIG. 2 may have another circuit configuration. (B) The reset unit 30 may have another circuit configuration. (C) The D-FFs 41 and 42 may be 1-bit or multi-bit shift registers. (D) One or more AND gates 43 and 44 may be provided depending on the signal to be detected.

[0011]

As described above in detail, according to the first and second aspects of the invention, in the external edge detection circuit, the edge detection signal is changed by the change of the input signal generated when the port function display signal changes. Since the reset circuit for preventing the generation is provided, the malfunction of the external edge detection circuit can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an external edge detection circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional microcomputer.

FIG. 3 is a block diagram of a port unit in FIG.

4 is a circuit diagram of an external edge detection circuit in FIG.

5 is a time chart of the external edge detection circuit of FIG.

FIG. 6 is a time chart of the external edge detection circuit shown in FIG.

[Explanation of symbols]

 30 reset unit 35 3-input NOR gate 36 2-input AND gate 37 D-FF

Claims (2)

[Claims] 1. A microcomputer provided with a port unit whose input / output functions are switched, the port unit being provided in a microcomputer for inputting and outputting a signal in synchronization with a clock signal, the port unit being synchronized with the clock signal. An external edge detection circuit for a microcomputer having an edge detection section for detecting an edge of a signal of the signal and causing the microcomputer to perform signal processing on the basis of the detection result, and switching an input signal from the port section and input / output of the port section. A detection unit that inputs a port function display signal that changes from time to time and detects a change in the input signal due to a change in the port function display signal to generate a reset signal, and the reset signal in synchronization with the clock signal. And a synchronization means for resetting the edge detection section by outputting Outside edge detection circuit of Yuta. 2. The external edge detection circuit for a microcomputer according to claim 1, wherein said detection means is composed of an AND circuit, and said synchronization means is composed of a flip-flop.