JPS63126018A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To attain low power consumption by providing each function block in a single chip microcomputer with a clock supplying gate or a power supplying switch. CONSTITUTION:A stand-by register 11 consisting of stand-by specification flags F1-Fn corresponding to peripheral circuits such as a timer circuit 4, a serial communication interface circuit 5 and I/O ports 6a-6d in the chip at the rate of 1 to 1 is formed. Specific addresses are assigned to the stand-by register 11, and when a CPU 1 specifies the address, a selection signal for specifying the register 11 is formed and the register 11 is specified to read out or write data from/in the register 11 through a data bus 7b. When the contents of respective flag bits F1-Fn of the register 11 are set up to '1', the peripheral circuits connected to the flags F1-Fn are held at an unactuated state and power or clock supply is interrupted.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is applicable to semiconductor integrated circuit technology and multifunctional logic L
The present invention relates to a technique that is particularly effective when applied to SI, for example, a technique that is effective when applied to a single chip microcomputer that incorporates a plurality of peripheral circuits.

[Prior art] In recent years, with the increasing functionality of microcomputers, RO
In addition to memories such as M and RAM, timer circuits, serial communication circuits, and DMA (direct memory access)
Single-chip microcomputers (hereinafter referred to as single-chip microcomputers) that incorporate a number of peripheral circuits such as controllers and A/D converters have become available.

[Problems to be solved by the invention] Although such high-performance single-chip microcontrollers are very convenient, depending on the user system, not all of the peripheral circuits installed may be necessary, and some circuits may not be used at all. It's coming.

However, conventional single-chip microcontrollers are configured to supply power supply voltage and clocks even to unused circuits. Therefore, as the functionality of microcomputers becomes more sophisticated, power consumption also increases.

Note that some CMOS microcomputers, such as the single-chip microcomputer HD6301 manufactured by Hitachi, Ltd., have a sleeve mode or a standby mode, and are capable of a low power consumption mode. ([Hitachi, Ltd. 1
Published September 982, rsEMIcONDUcTORDA
TA Bo.

K 8/16-bit Microcomputer” No. 277
(see page).

However, in the sleeve mode in the single-chip microcomputer, the operation of the MPU itself is stopped by an instruction called a sleeve instruction, and the peripheral circuits are operated during that time. Therefore, even if there are peripheral circuits that are not used, the power consumption there is not reduced.

On the other hand, in standby mode, when a dedicated control terminal called 5TBY is fixed to a low level, all internal clocks are stopped, and power is continued to be supplied only to the RAM and all other circuits are stopped, resulting in low power consumption. The aim is to Therefore, in standby mode, all functions of the microcontroller are stopped, and the operation of unnecessary circuits cannot be stopped. Also, in standby mode, the internal clock is stopped, so the CM
Even if it is applied to a microcontroller other than O8, such as an NMO8 type, the power consumption cannot be reduced.

An object of the present invention is to reduce the power consumption of a single-chip microcomputer incorporating a plurality of peripheral circuits.

Another object of the present invention is to enable reduction of power consumption in single-chip microcomputers other than CMOS microcomputers.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a clock supply gate or a power supply switch is provided for each functional block in a single-chip microcomputer, and a register that is made up of flag bits and is writable by a command is provided in a one-to-one correspondence with each of the functional blocks. The clock supply gate or the power supply switch is switched and operated according to the state signal of each bit of this register.

[Operation] According to the above-mentioned means, by specifying an unused functional block or peripheral circuit in a single-chip microcomputer using a register, it is possible to cut off the clock or power supply to the specified block and stop its operation. In addition to reducing the power consumption of single-chip microcontrollers with multiple built-in peripheral circuits,
It is possible to achieve the above object of reducing power consumption even in single-chip microcomputers other than MOS microcomputers.

[Embodiment] FIG. 1 shows an embodiment of a single-chip microcomputer to which the present invention is applied, and each circuit block shown in the figure is a single semiconductor chip such as a single-crystal silicon substrate. formed on top.

The single-chip microcomputer of this embodiment mainly includes, but is not particularly limited to, a microprocessor (hereinafter referred to as CPU) 1 that controls internal execution units, etc. according to a program, and a program ROM 2 that stores operating programs for this CPU. RA that provides the CPUI work area
M (Random Access Memory)3. A timer circuit 4 consisting of a reload timer or a programmable timer having a free-running counter, an input capture register, and an output conveyor register, etc.;
It consists of a serial communication interface circuit 5 that performs serial communication with external devices, parallel input/output ports 8 to 6d, etc., and these circuits are connected to each other via an internal address bus 7a and an internal data bus 7b. has been done.

The above-mentioned CPUI includes, but is not particularly limited to, a program counter that holds addresses of instructions and data to be read as a primary;
An instruction register from which program instructions are fetched in order, a control section consisting of a micro ROM in which a microprogram is stored or a random logic circuit, and which forms a control signal according to the instructions fetched into the instruction register, and various types such as an accumulator. It is composed of an execution unit consisting of registers and an ALU (arithmetic logic unit).

Of the input/output ports a to 6d, an address bus 7a and a data bus 7b are connected to port 6d.
An address bus 7a and a data bus 7b can be connected to the address bus 7a through a multiplexer 8. Furthermore, a mode switching circuit 9 is provided which determines the operating mode of the microcomputer after resetting by setting appropriate external terminals to predetermined states. The above input/output capotro d is
The port 6c functions as a port having a data input/output function or an address output function, and the port 6c functions as a port having a data input/output function or a function of multiplexing a data bus and an address bus.

This allows the address space of the single-chip microcomputer of this embodiment to be expanded.

In FIG. 1, reference numeral 10 indicates that the oscillation signal from an external crystal oscillator (or externally supplied clock CLK) is frequency-divided to generate an internal system clock φ1. φ2. This is a clock forming circuit that forms φ, a synchronizing signal E, etc. that is also output to the outside.

In this embodiment, the timer circuit 4, serial communication interface circuit 5, and
A standby register 11 is provided which includes standby designation flags F to Fn in one-to-one correspondence to peripheral circuits such as input/output capacitors h6a to h6d. This flag F1~
Fn is composed of a static or dynamic flip-flop. A specific address is assigned to this standby register 11 in the same way as the status register and control register in the timer and input/output ports, and when the CPU 1 outputs that address, the decoder 12 to form a selection signal SEL specifying standby register 11, specifying register 11,
Reading or writing can be performed via the data bus 7b. Reading or writing is specified using the read/write control signal R/W supplied from the CPUI.
However, this standby register 11 can be a write-only register seen from the CPUI.6 Furthermore, each flag bit F of the standby register 11
The contents of G1 to Fn are input to NAND gates G1 to Gn as status signals as shown in FIG. NAND
A control signal st supplied from the CPUI is commonly input to the other input terminals of the gates 01 to On. When a dedicated control terminal 5TBY provided on the chip is set to a low level, the control signal st is High level, NA
Standby register 11 among ND gates 01 to On
Only the output of the gate corresponding to the flag set to "1" is changed to low level.

Then, the output signals of these NAND gates 01~On are sent to the peripheral circuits PFR, ~P, such as the timer circuit 4 inside the chip.
For FRn, internal standby signal s t b y,
Supplied as ~5tbyn. Peripheral circuits to which a high-level internal standby signal is supplied are configured to completely stop their operations.

Therefore, if there is a peripheral circuit that is not used in a single-chip microcontroller, the corresponding flag in the standby register 11 is set to "1" by a program at system startup.
and lower the external terminal 5TBY to low level.

Then, the peripheral circuit specified by the standby register 11 does not operate at all, and power consumption is reduced accordingly.

In this embodiment, the operation of a desired peripheral circuit can be stopped at any time by dropping the terminal 5TBY to low level while the system is operating, but depending on the system, it is possible to stop the operation of a desired peripheral circuit from the beginning. In this case, it is sufficient to connect the external terminal 5TBY to the ground potential from the beginning.

Furthermore, instead of applying such a control signal 5TBY from the outside, the signal line for the internal control signal st is connected to the power supply voltage Vc.
c, or connect the status signals of each flag F1 to Fn of the standby register 11 to each peripheral circuit P.
Internal standby signal 5tby for FR, ~PFRn
It may be configured so that.

Possible methods for stopping the operation of each peripheral circuit using the internal standby signal 5tby include, for example, a method of cutting off the supply of clocks supplied to each circuit, and a method of cutting off the supply of power.

FIG. 3 shows - as an example a timer circuit 4 and a serial
A specific configuration of the operation stopping means in the communication interface circuit 5 is shown.

The timer circuit 4 includes a free running counter 41 that counts the clock φ1 supplied from the clock generation circuit 10.
and the counter 41 when the external input signal Tin changes.
The input capture register 42 captures and holds the count value of the input capture register 42, a flag indicating that the count value has been transferred to the input capture register 42, a flag indicating that the value of the counter 41 has become ro OOOJ, etc. It has a status register 43. A predetermined flag in the status register 43 is “1”
”, an interrupt signal IRQ is sent to the CPUI via gate G17.

Further, the registers 42, 43 and counter 41 are connected to the internal bus 7, and can be read/written by the CPU.

In this embodiment, when the internal standby signal 5tby output from the NAND gates Gz~Gn is set to low level, the AND gates G~G1° are closed and the internal clock output from the clock generation circuit 9 is activated. φ1.
φ2. The supply of φ□E to the timer circuit 4 is cut off, and the operations of the counter 41 and registers 42 and 43 are stopped.

At the same time, the gates G and G1, which are clocked inverters, are closed, and the input signal T from the outside is
The capture of in to the input capture register 42 and the transmission of the interrupt signal IRQ from the status register 43 to the CPUI are interrupted. Further, when the standby signal 5tby to the timer circuit 4 becomes low level, the MOS switches SL and S2 are turned on. This makes the input cab.

The input signal to the register 42 is fixed at a low level, and the node in the register 42 is placed in a floating state, thereby preventing a through current from flowing to a CMOS inverter or the like in the next stage. Furthermore, when the switch S2 is turned on, the interrupt signal transmission line 0 is pulled up to a high level. This prevents a low-level interrupt signal IRQ from being erroneously sent to the CPUI.

In addition to the free-running counter 41, input register 42, and status register 43 shown in FIG. 3, the programmable timer is provided with an output conveyor register and a comparator used for controlling the output waveform, for example. Sometimes. In that case, when the internal standby signal 5tby for the timer is set to low level, the clock supply to those circuit blocks is also cut off.

On the other hand, in the serial communication interface circuit 5 shown in FIG. 3, when the internal standby signal 5tby supplied to it is set to low level, the power supply voltage is supplied to various registers routed inside the circuit. The MOS switch S3 connected between the Vcc line 2o and the power supply voltage terminal Vcc is turned off. As a result, power supply voltage is no longer supplied to the receiving shift register 51, the transmitting shift register 52, etc., and the operation of the entire circuit is stopped.

In this way, the method of stopping the operation of the circuit by cutting off the supply of power supply voltage is effective if the circuit is an N-channel MO
This is effective when configured with only 8 FETs.

The receiving shift register 51 in the serial communication interface circuit 5 takes in the serial input data SDi sent from the outside, and converts it into a clock φ supplied from the clock forming circuit 10 (or a clock supplied from the outside). Shift in synchronization with

When the shift register 51 becomes full of input data, the input data is once transferred in parallel to the reception data register 53 and then read by the CPUI via the internal bus 7.

On the other hand, when transmitting serial data, the data to be transmitted is first transmitted via the internal bus 7 by the CPU, e.g.
The data is transferred in bytes to the transmission data register 52 and shifted in synchronization with the clock φ, thereby converting it into serial output data SDo and outputting it to the outside.

In addition to the above-mentioned registers 51 to 54, the serial communication inkface circuit 5 is provided with, for example, a control register and a status register, and when the standby signal 5tby is set to low level, data is sent to these registers. The power supply voltage supply is also cut off.

Further, in the above embodiment, the standby register 11 consisting of a flip-flop type flag that specifies whether to stop the operation of one peripheral circuit is provided.
Program ROM2 is EFROM or EEPROM
In a single-chip microcomputer configured with , each bit of the standby register 11 is configured with a nonvolatile storage element similar to a ROM memory cell, and flag bits corresponding to unused peripheral circuits are written in advance. You can do it like this.

Furthermore, the single-chip microcomputer of the embodiment is equipped with a programmable timer circuit 4, a serial communication interface circuit 5, and input/output capotros a to 6d as peripheral circuits, but in addition to the above-mentioned circuits, for example, The present invention can also be applied to a single-chip microcomputer having two types of timers such as a DMA controller, an A/D converter, a dual port RAM for parallel communication, or a reload timer.

Further, in the above embodiment, a standby register 11 consisting of flag bits corresponding to each peripheral circuit on a one-to-one basis is provided to specify whether or not to stop the operation of each peripheral circuit. If the peripheral circuit can be classified into multiple functional blocks instead of each peripheral circuit, a standby register consisting of flag bits with a one-to-one correspondence is provided for each functional block to determine whether or not to stop operation. It may be configured so that it can be specified. For example, taking a timer circuit as an example, in a system that uses only operations related to input capture registers and not operations related to output conveyor registers, only half of the circuits in the timer circuit are operated, The other half of the circuits can be configured not to operate with an internal standby signal.

As explained above, in the above embodiment, a clock supply gate or a power supply switch is provided for each functional block in a single-chip microcontroller, and flag bits are provided in a one-to-one correspondence with each functional block. A writable register is provided, and the clock supply gate or power supply switch is switched and operated by the status signal of each bit of this register, so the unused functional blocks or peripheral circuits in the single-chip microcontroller can be specified by the register. As a result, it is possible to cut off the clock or power supply to a specified block and stop its operation, which makes it possible to reduce the power consumption of a single-chip microcontroller with multiple built-in peripheral circuits.
This has the effect of reducing power consumption even in single-chip microcomputers other than MOS microcomputers.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, in addition to the operation stop mode for each peripheral circuit in the above embodiment, RA using an external terminal, which is performed in a conventional single-chip microcontroller,
It is possible to combine a standby mode in which the operation of circuits other than M is stopped and a sleep mode in which the operation of the CPU is stopped by an instruction, thereby further reducing the power consumption of the single-chip microcomputer.

In the above explanation, the invention made by the present inventor was mainly applied to a single-chip microcomputer, which is the background field of application, but the invention is not limited thereto.
specific integrated circuit
It consists of a microcomputer compatible with IT, various control LSIs, communication LSIs, and a plurality of other functional blocks, and can be generally used as a semiconductor integrated circuit with functions that are not used depending on the system.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, it is possible to reduce the power consumption of a single-chip microcontroller with multiple built-in peripheral circuits, and
Power consumption can also be reduced in single-chip microcomputers other than CMOS microcomputers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the overall configuration of a single-chip microcomputer according to the present invention, FIG. 2 is a block diagram showing an example of the configuration of its main parts, and FIG. 3 is a block diagram showing an example of the configuration of a single-chip microcomputer according to the present invention. FIG. 2 is a circuit diagram showing a configuration example of a timer circuit and a serial communication interface circuit. 4...Timer circuit, 5...Serial communication interface circuit, 7...Internal bus, 7a...Address bus, 7b...Data bus, 11...Standby -Register, 12...Decoder, 51...Transmission shift register. 52...Reception shift register, F1~Fn"...
flag. Figure 1

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit having a plurality of functional blocks, a block specifying means consisting of a group of flags corresponding to each functional block is provided, and the operation of the functional block specified by the block specifying means is stopped. A semiconductor integrated circuit characterized in that it is configured to 2. The semiconductor integrated circuit according to claim 1, wherein the operation of the functional block specified by the block specifying means is stopped by cutting off the supply of a clock signal to the functional block. circuit. 3. The semiconductor integrated circuit according to claim 1, wherein the operation of the functional block specified by the block specifying means is stopped by cutting off the supply of power supply voltage to the block. .