JPS6227408B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit, and relates to a microprocessor constructed by MOSLSI or the like.
It is related to the internal system bus (system bus) of the cessor and its peripheral LSIs, and its purpose is to reduce wasteful power consumption.

That is, in the present invention, when the system bus is cut off from data from internal registers or external data and is in an independent state, a control circuit connected to the system bus sets the system bus to a high level or a low level. In addition, when data is transferred to the system bus, static current paths are eliminated by keeping the data statically in the state, and when data is transferred to the system bus, whether the data is at a high level or a low level, there is no static current path. It provides a system bus that reduces the power consumption of circuits.

FIG. 1 is a schematic diagram of a portion related to a system bus of an example of a microprocessor. 1 is a system bus represented by an internal address bus or an internal data bus, which consists of eight lines in an 8-bit microprocessor, for example. 2 and 3 indicate registers such as an accumulator, stack pointer, and index register, or a program counter, and 4 indicates an ALU (alithmetic logic unit). 5 is a buffer for transferring the contents of system bus 1 to an external bus; 6, 6', and 7 are bidirectional buses; 8, 9, and 10 are input/output buses for ALU 4; and 11 is another internal system different from 1. This is also an 8-bit bus consisting of 8 lines. 13 is an instruction register that holds instructions from the external data bus 12; 14 is an instruction register through which the contents of the instruction register 13 are decoded through the internal bus 15;
This part outputs a control signal through bus 8, and this control signal is involved in buses 6 to 10 and controls data transfer. The control signal of the bus 18 is also outputted via the interrupt logic or restart logic circuit sections 17 and 14 when an interrupt or restart 16 occurs.

Basically, the above operation is based on the timing generator 20 outputting timing via the line 21 based on the basic clock 19, and the operation is performed based on this timing.

In the configuration shown in Figure 1, system buses 1, 1
1 means that when buses 6, 7, and 10 are in a non-conductive state, that is, when the system bus is independent from registers 2, 3, or ALU 4, etc., all or most of each bit of system buses 1 and 11 is set. It is convenient for the portion to be held at a high level or at a low level. For example, if a vector address method is used when an interrupt or restart occurs, for example, when system bus 1 is an internal address bus, control signals are output via bus 18 depending on the type of restart or interrupt. If system bus 1 is not held at high or low level in advance,
Each bit of the system bus must be controlled, making the logic extremely complex.

On the other hand, if system bus 1 is held in the state of "1", for example, 11111110 (for 8 bits)
In order to output , only the lower one bit needs to be "0", which simplifies the logic.

An example of an n-channel MOS LSI conventionally used to realize such a system is shown in FIG. 2.

FIG. 2 shows the structure of the register portion connected to each 1-bit portion of system buses 1 and 11 in FIG. 1, where 33 is one line of system bus 1;
34 indicates one line of the internal system bus 11. Transistors 44 and 46 serving as transfer gates constitute a bus 6', and transistors 45 and 47 constitute a bus 6.

In FIG. 2, further control signals 36 to 39
In FIG. 1, corresponds to a part of the control signal output from the bus 18, 35 is a precharge signal,
40 to 51 are n-channel MOS transistors;
Reference numerals 31 and 32 represent the input and output parts of the register 2a, respectively, and 52 represents a control signal for forcibly lowering the control signal lines 36 to 39 to the ground level. Note that V _DD is a power supply voltage. For convenience when explaining the operation of FIG. 2, the clock signals are φ ₁ and φ ₂ as shown in FIG. 3.
Consider the two-phase case. Of course, the same can be considered in the case of a multiphase clock having three or more phases having clocks corresponding to two phases φ ₁ and φ ₂ .

Now, assume that the control signal lines 36 to 39 can be synchronized with φ ₁ and become high level during the high level section of φ ₁ , and the precharge signal 35 and the control signal 52 are signals equivalent to φ ₂ synchronized with φ ₂ . If this is the case, a valid signal will be placed on the system buses 33 and 34 in synchronization with _φ1 . Now, the second
If the circuit shown in the figure operates dynamically, the pull-up transistors 42 and 43 are not essentially necessary, but in the case of static operation, the transistors 42 and 43 are essentially necessary.
In this case, for example, when the control signal line 37 becomes high level at φ ₁ , the transistor 45 becomes conductive, and the contents of the register 2 are outputted to the system bus 33 via its output section 32, when the output is at a low level, In the interval of φ ₁ , transistors 43, 4
5 and the driver transistor at the output of resistor 2, a static current path occurs, resulting in an increase in the power consumption of the entire system.

In view of the above-mentioned problems, the present invention provides a system bus circuit that does not cause static current paths except for leakage current, and when the system bus is at a potential logically different from the power supply or ground potential. Or, it interrupts the current path from ground to the system bus.

For example, as is well known in complementary MOS circuits, there is no current path in the static circuit, so
It is possible to provide a circuit with extremely low power consumption compared to an n-channel MOS circuit or the like.
Therefore, if the present invention is further applied to circuits around a system bus using complementary MOS circuits, it is possible to eliminate static current paths and provide an integrated circuit with extremely low power consumption.

FIG. 4 shows an embodiment of the circuit of the present invention.

Note that in FIG. 4, parts showing operations and parts similar to those in FIG. 2 are given the same numbers as in FIG. 2, and redundant explanation will be omitted. For convenience, it is assumed that the basic clock operates as a two-phase clock of φ ₁ and φ ₂ as shown in FIG. Similar to the case of FIG. 2, the case of a multiphase clock of three or more phases having clocks corresponding to two phases φ ₁ and φ ₂ can be considered in the same way.

Note that the transfer gate composed of transistors 40, 41, 44 to 47 is an n-channel.
The register 2 and inverters 60, 61, which may be composed of MOS type transistors or N-channel and P-channel transistors, are supplied with input signals from lines 34, 32 and are complementary type transistors.
Consists of MOS transistors, transistor 6
2 and 63 are lines 34 that constitute the system bus;
33 and the power supply _VDD , and is composed of a P-channel transistor.

Inverters 60, 61 and transistor 6
2 and 63 form two control circuits, which in the case of FIG. 4 serve to maintain the system buses 33 and 34 at a high level. In Fig. 4, the control circuit is simply composed of three transistors, and six
0 and 61 are CMOS inverters, and 62 and 63 are switching P-channel MOS transistors.

The operation of FIG. 4 will be explained below. When clock _φ2 applied to line 35 is at a high level, precharge signal 35 causes system buses 33 and 34 to be at a high level. Since this state is applied at low level to the gates of P channel transistors 62 and 63 through inverters 60 and 61, system buses 33 and 34 are also at high level due to these transistors. In this state, positive feedback is applied by the inverters 60, 61 and the transistors 62, 63, so that it is held at a high level when the system bus is disconnected from the register.

When the clock is at a high level of _φ1 , for example, the control signal 37 causes the transfer gate 4 to
Consider the case where the contents of register 2 are outputted through output unit 32 via 5. When the contents of the register are at a high level, the driver transistor of the output section 32 of register 2 is also in a cut-off state, so
System bus 33 remains held high and there is no DC path from power supply to ground.

When the contents of the register 2 are at a low level, the driver transistor of the output section 32 of the register 2 becomes conductive. However, when the system bus 33 becomes low level, a high level voltage is applied to the gate of the P channel transistor 63 via the inverter 61, so that the transistor 6
3 is in a cut-off state. Therefore, a DC path from the power supply V _DD to the system bus 33 no longer occurs.

As described above, whether data is connected to the system bus or not, no current path flows from the power supply to the ground via the system bus.

The example in Figure 4 is for the case where the system bus is connected to the power supply V _DD , but it is also possible to connect the system bus to the low-level ground potential GND, for example, and to determine the so-called system bus potential by discharge. An example is shown in FIG.

In FIG. 5, the same parts as in FIG. 4 are given the same numbers as in FIG. 4, and redundant explanation will be omitted.
In FIG. 5, the P channel transistor 6 of FIG.
2, 63 are n-channel transistors 64, 65
, transistors 40, 41, 64, 6
It is sufficient to change one terminal of 5 from the power supply voltage (V _DD ) to the ground voltage (GND). The operation is the same as when the system buses are held at a high level; when the system buses 33 and 34 become high level, the transistors 64 and 65 are turned off, and the connection between the system buses 33 and 34 and GND is cut off. , GND
No current flows to.

In addition, as shown in FIG. 6, P channel transistors 62 and 63 for switching are shown in FIG.
Even if the CMOS inverters 66 and 67 are used, the operation is exactly the same. Furthermore, as shown in Figure 7,
N-channel switching transistor 6 in the figure
CMOS inverter 66, 67 instead of 4, 65
Using this, a configuration as shown in FIG. 7 can be obtained.

As can be seen from the above, the present invention realizes a circuit for holding the system bus at a high level or low level with an extremely simple circuit configuration, and when the system bus is at a logic potential different from the power supply potential or ground potential, the power supply Alternatively, it cuts off the current path between the ground and the system bus, making it possible to operate with extremely low power consumption.

[Brief explanation of the drawing]

Figure 1 is a schematic circuit configuration diagram of the system bus related part of a microprocessor, Figure 2 is a conventional specific circuit diagram of the system bus related part, Figure 3 is a diagram showing the basic clock, and Figure 4 is a diagram related to the system bus. Part 5 of a circuit diagram of an embodiment of the present invention;
6 and 7 are circuit configuration diagrams of other embodiments of the present invention. 1, 11...System bus, 2...Register,
33, 34... System bus line, 44, 4
5...MOS transistor, 60, 61...
CMOS inverter, 62, 63...P channel
MOS transistor, 64, 65...n channel MOS transistor, 66, 67...CMOS inverter.

Claims (1)

[Claims] 1. A precharge transistor connected to an internal system bus in an integrated circuit, a switching transistor connected between the system bus and a power supply or between the system bus and ground, and a signal from the system bus. a control unit that opens and closes the switching transistor according to the value of the signal applied thereto; a control transistor that transmits and receives signals from and to the system bus; and the precharge transistor and the control transistor. A basic clock for timing generation is provided, and during the precharge period, the potential of the system bus is maintained at the power supply potential or ground potential by the precharge transistor, and outside the precharge period, the control transistor is becomes active and the potential of the signal to the system bus is logically the same potential as the power supply potential or the ground potential, the switching transistor and the control unit hold the potential of the signal on the system bus. When the potential of the signal to the system bus is logically different from the power supply potential or ground potential, the switching transistor is made inactive, and the current from the power supply potential or ground potential to the system bus is An integrated circuit characterized by being formed by cutting off a circuit. 2. The integrated circuit according to claim 1, wherein the control section comprises an inverter.