JPH0555960B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an internal register of a semiconductor integrated circuit device with initial value setting input.

[Conventional technology]

Examples of internal registers in a conventional semiconductor integrated circuit device with initial value setting input are shown in Figures 2a and b.
I will explain about it. In the figure, 1 and 2 are inverter gates, the output of inverter gate 1 is connected to the input of inverter gate 2, and the output of inverter gate 2 is connected to transmission gate 3.
is connected to the input of the inverter gate 1 via the inverter gate 1. Also, the input of inverter gate 1 is DATA.
An input 4 is connected via a transmission gate 5. In other words, 6 is a latch circuit composed of inverter gates 1 and 2 and transmission gates 3 and 5, and its input is
It is controlled by the WRITE signal and its inverted signal. 7 is an enhancement type N-channel MOS whose source is connected to the low potential side.
In the example shown in FIG. 2a, the drain of the transistor 7 is connected to the input of the inverter gate 1, and in the example shown in FIG. 2b, the drain of the transistor 7 is connected to the input of the inverter gate 2. There is. Further, an initial value setting signal is connected to the gate of the transistor 7.

Next, the operation will be explained.

In the example shown in FIG. 2a, when the initial value setting signal is "H", the input of the inverter gate 1 is pulled down to the low potential side by the transistor 7, and the output 8 of the latch circuit 6 is set to "H". This state is maintained while the control signal WRITE is "L". In other words, the example shown in FIG. 2a functions as a register that is set to "H" in the initial state.

In the example of FIG. 2b, since transistor 7 is connected to the input of inverter gate 2,
When the RESET signal is “H”, inverter gate 2
The input of the latch circuit 6 is pulled down to the low potential side, and the latch circuit 6
The output 8 of is set to "L". In other words, Figure 2b
The example works as a register that is set to "L" in the initial state.

[Problem that the invention seeks to solve]

In a conventional semiconductor integrated circuit device, the register is configured as described above, and the transistor 7
The initial value of the register, "H" or "L", is determined by the connection location of the drain of the register, so if you want to change the initial value due to changes in specifications, etc., you must change the pattern of the semiconductor integrated circuit device. Not necessarily,
There was a problem that it was difficult to change the initial values.

This invention has been made to solve the above-mentioned problems, and aims to provide a semiconductor integrated circuit device in which initial values can be easily changed without changing the pattern of the semiconductor integrated circuit device. purpose.

[Means for solving problems]

In the semiconductor integrated circuit device according to the present invention, the set value of the register in the initial state is determined according to the data in the built-in ROM.

[Effect]

In this invention, the initial state setting value of the register is determined according to the data in the built-in ROM, so that the initial state setting value can be easily changed without changing the pattern of the circuit device.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor integrated circuit device according to an embodiment of the present invention, in which 6 indicates inverter gates 1 and 2 and transmission gates 3 and 5.
This is the same latch circuit as shown in FIGS. 2a and 2b. 7 and 8 are enhancement type N channels.
It is a MOS transistor, and the drain of transistor 7 is connected to the input of inverter gate 1,
The drain of the transistor 8 is connected to the source of the transistor 7, and the source is connected to the low potential side.
9 and 10 are enhancement type P channel MOS
The drain of the transistor 9 is connected to the input of the inverter gate 1, the drain of the transistor 10 is connected to the source of the transistor 9, and the source is connected to the high potential side. Also,
Built-in ROM is installed at the gates of transistors 8 and 10.
Output 12 of bits with data of 11 predetermined locations
is connected, and in this embodiment, the second bit data output is connected. Also transistor 7
A signal which is an initial state setting signal is connected to the gate of the transistor 9, and a signal which is an initial state setting signal is connected to the gate of the transistor 9.
A signal obtained by inverting the RESET signal by an inverter gate 13 is connected. In this way, these transistors 7, 8, 9, and 10, built-in ROM 11, and inverter gate 13 constitute initial state setting input means.

Next, the operation will be explained.

If the data in built-in ROM11 is “1”,
Since the ROM data output 12 is "H", the transistor 8 is turned on and the transistor 10 is turned off. When the signal becomes "H" in this state, both transistors 7 and 9 are turned on, but since transistor 8 is on and transistor 10 is off, the input of inverter gate 1 is pulled down to the low potential side. As a result, the DATA output 8 of the latch circuit 6 is initially set to "H".

Conversely, when the data in the built-in ROM 11 is "0", the ROM data output 12 becomes "L",
Contrary to the above, transistor 10 is turned on and transistor 8 is turned off. Therefore, due to the "H" signal input, the input of the inverter gate 1 is pulled up to the high potential side, and as a result, the latch circuit 6
The DATA output 8 of is initially set to "L".

Further, at this time, since the WRITE signal of the latch circuit 6 is "L" and the signal is "H" except when data is input, the initial setting value is maintained even after the input is released to "L".

In this way, the register of this embodiment has its built-in
The data in ROM11 is “1” and the initial state is “H”
In addition, since it functions as a register that is set to the initial state "L" at "0", the initial state setting value can be easily changed by changing the data in the built-in ROM without changing the circuit device pattern. When applied to various devices such as microcomputers, register initial values suitable for usage conditions can be easily set by a program.

Note that in the above embodiment, the transistors 9 and 10
is connected to the high potential power supply side, and the transistors 7 and 8 are connected to the low potential power supply side, but this may be reversed. Also, in the above embodiment, the initial state setting input means is connected to the inverter gate 1. Although this is connected to the input of the inverter gate 2, it may also be connected to the input of the inverter gate 2. In these cases, if the built-in ROM data is "1" and the initial state is "L", the built-in ROM data is "1" and the initial state is "L". It operates as a register whose data is "0" and its initial state is set to "H".

Further, in the above embodiment, the transistor 7,
Of course, even if each of transistors 8 and each of transistors 9 and 10 are arranged in reverse, the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the semiconductor integrated circuit device of the present invention, the initial state setting value of the register is built-in.
Since the determination is made according to the data in the ROM, there is an effect that the initial state setting value can be easily changed without changing the pattern of the semiconductor integrated circuit device.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a register of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIGS. 2a and 2b are circuit diagrams showing registers of a conventional semiconductor integrated circuit device. In the figure, 1, 2, 13 are inverter gates, 3, 5 are transmission gates, 7, 8
is an enhancement type N-channel MOS transistor, and 9 and 10 are enhancement type P-channel MOS transistors.
MOS transistor 11 is a built-in ROM. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device comprising a register having a latch circuit and means for inputting and setting an initial state of the register, the initial state setting input means holds predetermined data. It is equipped with a built-in ROM and an output circuit that receives an initial state setting signal and outputs "H" or "L" data according to the data of the built-in ROM at the stage before the data output terminal of the latch circuit. A semiconductor integrated circuit device characterized by: 2 The above output circuit has its output terminal and high potential power supply (or low potential power supply)
two P-channel MOS transistors connected in series between the output terminal and the low potential power supply (or high potential power supply)
and two N-channel MOS transistors connected in series between the P-channel MOS transistor and the N-channel MOS transistor.
The output of the P-channel MOS transistor and the N-channel MOS transistor are connected to each other, and initial state setting inputs are connected to the gates of the other P-channel and N-channel MOS transistors via an inverter and as they are, respectively. Semiconductor integrated circuit device.