JPS59153225A - Semiconductor integrated circuit device and information processing system using the device - Google Patents

Abstract

PURPOSE:To attain synchronization simply without increasing the number of external terminals and to improve information processing ability by actuating the titled system selectively by a clock signal from a built-in oscillation circuit or a clock signal from the external. CONSTITUTION:The titled system is actuated selectively by a clock signal from the built-in oscillation circuit or a clock signal from the external. For instance, an oscillation output of the oscillation circuit consisting of an amplifier circuit 6, etc. is inputted to a frequency dividing circuit 7, which forms a clock signal necessary for the operation of a microprocessor CPU1 and supplies the clock signal to a gate circuit 8. On the other hand, a clock signal is applied to the gate circuit 8 from an external terminal and the gate circuit 8 sends any one of these clock signals selectively. When a clock signal is formed by the built-in oscillation circuit, a quartz oscillator or the like is connected to terminals P1, P2 to form the oscillation circuit. When the CPU1 is to be actuated by the clock signal supplied from the external, earth potential is connected to the external terminal P2 to apply a fixed voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device including a microprocessor (CPU) and an information processing system using the same.

2. Description of the Related Art Conventionally, microprocessors are known that operate selectively using an oscillation output from a built-in oscillation circuit or a reference oscillation signal supplied from an external terminal.

By the way, an information processing system is being considered that uses a plurality of microprocessors to increase its information processing capability. In this case, it is necessary to operate multiple microprocessors synchronously.

In conventional microprocessors, the oscillation signal is divided by a frequency divider circuit to form the internal clock signal, so even if the same oscillation signal is used, the initial value of the frequency divider circuit is undefined, so both microprocessors Even if the frequencies of the clock signals are the same, the phases are not necessarily the same, so they have the disadvantage that they cannot be operated reliably in synchronization.

An object of the present invention is to provide a semiconductor integrated circuit device including a microprocessor that can be selectively operated using a clock signal generated by a built-in clock generation circuit or a clock signal supplied from an external source and can be easily synchronized. It is about providing.

Another object of the present invention is to provide a semiconductor integrated circuit device that can achieve the above synchronization without increasing the number of external terminals.

Another object of the present invention is to provide an information processing system that can improve information processing ability with a simple configuration.

Further objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1 shows a block diagram of an embodiment in which the present invention is applied to a one-chip microcomputer. In the figure, each circuit block surrounded by broken lines...
The circuit is formed on a semiconductor substrate, such as silicon, by known semiconductor integrated circuit manufacturing techniques.

Denoted by symbol 1 is a microprocessor CP'
It is U. The main constituent blocks of this microprocessor CPU are illustrated as a representative example. That is, the microprocessor CPU has an accumulator A,
Index register X, condition code register cc, stack pointer SP, program counter P
It is composed of CH, PCL, arithmetic and logic unit ALU, cPU controller CPUC0N'T, etc. Since the configuration of such a microprocessor CPU is well known, detailed explanation thereof will be omitted.

The symbols 2 to 5 are input and output ports, and the symbols 2 to 4 are the input and output ports.
A data direction register RA or RC is provided,
Used as an input/output boat. Also, what is indicated by symbol 5 is an input-only port.

What is indicated by the symbol 6 is an amplifier circuit for constructing an oscillation circuit, and although not particularly limited, an oscillation operation is performed by connecting an external crystal resonator or the like. This oscillation output is input to a frequency dividing circuit 7, which forms a lock signal necessary for the operation of the microprocessor CPU, and sends it out through a gate circuit 8. A clock signal supplied from an external terminal is applied to the gate circuit 8, and one of the clock signals is selectively output.

A RAM (Random Access Memory) is indicated by the symbol 9 and is mainly used as a temporary data storage circuit. Also, what is indicated by the symbol 1° is a ROM (read only memory) in which programs for various information processing are written.

The above circuit blocks are connected to each other by a bus BUS with the microprocessor CPU as the center. This bus BUS includes an address bus and a data bus.

FIG. 2 shows a circuit diagram of an embodiment of a circuit for selectively switching the clock signal.

The output and input of the inverting amplifier circuit 6 are respectively connected to an external terminal P.
I, connected to P2. These external terminals PI, P
Oscillation operation is performed by connecting a crystal resonator or the like to 2. The output signal of the amplifier circuit 6 is input to the inverter IV2, where it is amplified and waveform-shaped and is transmitted to the frequency divider circuit 7. The clock signal φ formed by this frequency dividing circuit 7
On the one hand, a is input to an AND game (G2) that constitutes the gate circuit 8. Further, the clock signal φa is
On the other hand, 3-state (tri-state) output cover sofa B
The signal is sent from the external terminal P3 through the terminal P3.

Further, the clock signal φ supplied from the external terminal P3 is
b is input to the AND gate G1 constituting the gate circuit 8. In order to control these AND gates Gl, G2 and the output buffer AB, the next level determination circuit LV is provided.

That is, the signal at the external terminal P2 is not particularly limited, but the signal at the inverter IV3. The signal is transmitted to the latch circuit formed by IV4. This launch circuit operates as a Schmitt trigger circuit utilizing hysteresis characteristics formed by its positive feedback operation. The output signal C of the level determination circuit LV is used as a control signal for the AND game Gl and the output buffer B. The inverted signal passed through the inverter IV'5 is used as a control signal for the AND gate 1-02.

Then, the AND gate G1. ．． The output of G2 is OR
The output signal φ is input to the gate G3 and is transmitted to the C, PU controller CPUCONT as the clock signal.

The operation of this embodiment circuit will be explained with reference to the operation diagram of FIG.

The figure shows the input/output transfer characteristic A of the inverting amplifier circuit and its DC feedback characteristic B, and the input bias point is determined at the intersection P thereof. For example, when forming the clock signal φ using the built-in oscillation circuit, both the terminals Pi and P
A crystal resonator or the like is connected to 2 to form an oscillation circuit. In this case, an oscillation signal O8C centered at the intersection P is obtained. If the bias point P is the logic of inverter IV3,
The output of the inverter IV3 forms an output signal that is amplified to a lower level as a whole. Inverter IV4 further amplifies the amplified signal of inverter IV3 and provides positive feedback to the human power of inverter IV3.

As a result, the high level side threshold voltage VT+ becomes high as shown in the figure, and the low level side threshold voltage VT- for inverting this becomes low as shown in the figure, and has hysteresis characteristics. At this time, inverter IV3. When the low level side threshold voltage VT- and the high level side threshold voltage VT+ of the Schmitt circuit constituted by IV4 are at the levels shown in FIG.
The output of 3 becomes low level, and then the oscillation circuit O3C
Since the amplitude of inverter Iv3 does not become smaller than VT-, the output of inverter Iv3 becomes low level.

Therefore, the output C of the inverter IV3 becomes a low level (logic "0"), and the output d of the inverter IV5 becomes a high level (logic "1"). Therefore, the AN and D gates G2 are opened and the AND gate G1 is closed. As a result, the clock signal φa formed by the frequency dividing circuit 7 operating in response to the oscillation output is applied to the AND gate G.
2 and the OR gate G3 to the CPU controller CPUCONT. Furthermore, due to the low level of the output signal C of the inverter IV3, the output pants 1
B operates to send out the clock signal φa formed by the frequency dividing circuit 7 from the external terminal P3.

On the other hand, when the microprocessor CPU is operated by the clock signal φb supplied from the outside, the external terminal P2 is connected to the ground potential and a fixed voltage is applied. As a result, the latch circuit sets its output signal C to a high level, so that, contrary to the above case, the AND gate G1 is opened and the AND gate G2 is closed. In addition, since the output signal C becomes high level and puts the output huffer B in a high impedance state, the clock signal φb' from the external terminal P3 passes through the AND gate Gl and OR gate G3 to the CPU controller °cp. , U
c, communicated to ONT. In the semiconductor integrated circuit device including the microprocessor CI)U of this embodiment, the external terminals PI and P2, which constitute the oscillation circuit, depend on whether they are connected to components or whether they are supplied with the ground potential of the circuit, as described above. , can be selectively operated using internal or external clock signals. In this embodiment, the microprocessor CPU can be operated with the above two types of clock signals φa or °φb very easily using the minimum number of external terminals required.

In this case, the clock signal from the external terminal P3 is directly used as the clock signal of the microprocessor CPU, so by inputting the clock signal used for another microprocessor CPU, that microprocessor CPU and this implementation The microprocessor CPU built into the example semiconductor integrated circuit device can be synchronized and operated.

Further, as shown in the block diagram of FIG. 4, using the two semiconductor integrated circuit devices LSII:LSI2 of the above embodiment,
When parallel information processing is performed by two microprocessors CPU, the external terminals PI and P2 of one semiconductor integrated circuit device LSII are connected to external components for configuring an oscillation circuit.
For example, a crystal resonator X and capacitors CI and C2 are connected. Then, the microprocessor CPU is operated with the clock signal φa formed by this oscillation signal, and the clock signal φa is sent from the external terminal P3, so that the external terminal P3 of the semiconductor integrated circuit device LSII and the other semiconductor External terminal P of integrated circuit device LSI2
3, and this semiconductor integrated circuit device LS
External terminal P of I2 2. Apply ground potential to As a result, the clock signal φa formed in one of the semiconductor integrated circuit devices is inputted to the microprocessor CPU of the other semiconductor integrated circuit device LSI2, so that the microprocessor CPU of both semiconductor integrated circuit devices LSII and LSI2 is inputted to the microprocessor CPU of the other semiconductor integrated circuit device LSI2. It can be operated synchronously. Since the semiconductor integrated circuit device of this embodiment is configured to operate with the above two types of clock signals, one type of semiconductor integrated circuit device can be used as a master semiconductor integrated circuit device in a parallel information processing system as well as a slave semiconductor integrated circuit device. Since it can also be used as a circuit device, its versatility can be increased.

The invention is not limited to the above embodiments.

In the example circuit shown in Fig. 2, if there is sufficient number of terminals, the output terminal and input terminal for the clock signal may be provided separately, or the terminal for the switching signal of the gate circuit may be newly provided. good.

Further, in the case where the oscillation terminal and the control terminal are shared as in the above embodiment, the level determination circuit LV may be any circuit as long as it performs the same operation as above.

Semiconductor integrated circuit devices to which this invention is applied include the above-mentioned one-chip microcomputer, as well as the above-mentioned ROM.
, or may be a semiconductor integrated circuit device constituting a so-called one-chip microprocessor in which a RAM is a separate semiconductor integrated circuit device. Furthermore, these microcomputers or microprocessors can be implemented in various embodiments, such as by adding an A/D converter, a timer circuit, etc.

[Brief explanation of drawings]

Fig. 1 is a program diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing an embodiment of a circuit for selectively switching the clock signal, and Fig. 3 is an explanatory diagram of its operation. FIG. 4 is a block diagram showing another embodiment of this invention. l...MicroProcera CPU, 2-5...port,
6... Inverting amplifier circuit, 7... Frequency divider circuit, 8... Gate circuit, 9... RAM, 10... ROM Fig. 1 Fig. 2 P/ and 1 Fig. 3 ott7 Fig. 4

Claims (1)

[Claims] 1. A reference oscillation circuit, a frequency dividing circuit that receives the oscillation output and forms a predetermined clock signal, a first external terminal that sends this clock signal to the outside, and the frequency divider A gate means for selectively sending out a clock signal formed by the circuit and a clock signal supplied from a second external terminal, and a microprocessor operating in response to the clock signal passed through the gate means. A semiconductor integrated circuit device comprising: 2. The first external terminal and the second external terminal share the clock signal formed by the frequency dividing circuit by using a three-state output circuit. A semiconductor integrated circuit device according to scope 1. 3. The above semiconductor integrated circuit device includes ROM and RAM.
Claim 1 or 2 is characterized in that it has a built-in 1-chip microcomputer.
The semiconductor integrated circuit device described in Section 1. 4. The reference oscillation circuit has an external terminal for connecting external components, operates as an oscillation circuit by connecting a predetermined electronic component to this external terminal, and fixes this external terminal at a predetermined signal level. The semiconductor integrated device according to claim 1, 2 or 3, wherein the fixed signal level is used to form a control signal for switching the gate means. circuit device. 5. A reference oscillation circuit, a frequency dividing circuit that receives this oscillation output and forms a predetermined clock signal, a first external terminal that sends this clock signal to the outside, and a clock signal formed by the frequency dividing circuit. and a clock signal supplied from a second external terminal, and a microprocessor that operates in response to the clock signal passed through the gate means. the clock signal sent from the first external terminal of the first semiconductor integrated circuit device to the second external terminal of the second semiconductor integrated circuit device, and the microprocessor in both semiconductor integrated circuit devices. An information processing system that operates synchronously using the same clock signal. 6. Information processing according to claim 5, wherein the first and second semiconductor integrated circuit devices each include a built-in ROM and a RAM, and constitute a one-chip microcomputer. system.