JPS6275822A - Computer system - Google Patents

Abstract

PURPOSE:To reduce the load of a programmer by providing a clock selecting circuit and a clock switching program and giving the dynamic change to the clock speed at the part of a software timer. CONSTITUTION:Both clocks A and B are supplied to a clock selecting circuit 1 via lines 2 and 3 respectively and either one of both clocks is usually delivered through a line 5. When the input clock is changed, the control signal SEL of a line 4 is allocated to a certain port address. Then an access is given to the relevant port by a program and the signal SEL is inverted. In other words, the count frequency is set at a part equivalent to a timer (loop) by a prepared program and an access is given to the port to which the circuit 1 is allocated. Then this port is switched as necessary to the logic clock obtained when the program is designed. Thus the clocks are fixed during an actual loop and the replacement of programs is omitted. As a result, the load of a programmer is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a computer system having a software timer.

[Technical background of the invention and its problems]

The speed of microprocessors (MPUs) is increased during the development process. For example, Inch/I/'s 16-bit MPU8086H with a f5MHz (megahertz) clock was announced, and after 1970, it was upgraded to an 8MHz clock. Di0g's 8-bit MPU,
The Z80 started with the 2M82 version, which was also upgraded from 4MHz to 6MHz. These MP
In the next system that uses U, the MPU performance [ftset”c
It is customary to increase the r-track frequency to improve system performance.

The only problem in this case is the software timer routine. In other words, when waiting for a certain period of time (for example, to ensure the settling time of a floppy disk drive), the MPU clock is set to 4M.
The number of loops is 1:2 for Hz and BMHz.
Must be. Furthermore, if the number of loops is set assuming 8MH2, the wait time will be twice as long for 4MH2. Therefore, it is necessary to change the number of loops each time the number of cycles changes, which is a burden on the programmer.

[Purpose of the invention]

The present invention is made based on the above circumstances O;
The object of the present invention is to provide a computer system that reduces the burden on a computer programmer by dynamically changing the clock speed of a software/ware timer section.

[5^ Akira's main message] In order to achieve the above purpose, Motosukeaki added all the selection circuits to the conventional components of this Hashi computer system, and saved human power. If one of the clocks of Haji is configured to supply σA (y) to the unit, then after setting the count value,
The above selection circuit? , lJ jM accesses the board that is set, changes it to one for the clock and timer, and even after the timer ends, performs the process of switching the -clock clock.5, according to the program, Divemic C' The clock speed of the software timer is fixed, eliminating the need to recreate the software timer at different clock speeds.

This eliminates the need to change the program and reduces the burden on the software programmer.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, J is a clock selection circuit, and clocks A and B with different frequencies are connected to lines 2 and 3, respectively.
Supplied via. The signal supplied via line 3 is a control signal, and one of the clocks A and H is selectively output via line 5.

FIG. 2 shows the operation flow of a program in which the clock speed of the timer section is fixed. Is the program assigned the clock selection circuit shown in the first factor after setting the count? -), the clock is switched to the clock for the timer, and the clock is switched to the original clock after the timer ends. Details will be described later. .

Figure 3 shows the clock selection circuit shown in Figure 1! FIG. 2 is a diagram showing a specific circuit configuration. Clock selection (path 1 is 5
D-type flip-flops I1.12.13,14
．． 15, two OR gates 16, 17. and one AND gate 18. In the figure, the symbols or numbers that are the same as those in Figure 1 are II.
', l It is the same as that of J Enoki. In addition, Dn is data signal), and OUT is 41 that arrives due to the CIUT command.
Indicates the number.

FIG. 4 is a timing chart showing the operation of the embodiment of the present invention.
). In the figure, blocks or lines numbered the same as number 9 in FIG. 3 are the same as those in FIG. 3.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail. First, the general operation will be explained using FIG. 1 and the second factor. The clock selection circuit 7 is supplied with a clock Δ and a clock B, respectively, via lines 2.3. Clog, N.
and clock B are clocks with different frequencies. usually,
10,000 clocks, either clock A or clock B (
The CPU is operating on the g output (line 5). To switch to the other clock, allocate the control signal (line 4) to a certain boat address, access that port using a program, and invert the control signal fg.

21J, a timer (loop) in a certain Tumigram
After setting the count number in the part corresponding to (: wa day in the flowchart shown in Figure 2 C'ζ7 bus), the clock selection time w! shown in Figure 1 is set. ! The clock during the actual loop is fixed by accessing the port to which rL is assigned and switching the processing clock at the time of program design as necessary. Once the loop is complete, activate the boat again! Processing that continues after switching to the normal CPU clock? Let's do it.

The operation of switching from 1 to 1 will be explained in detail with reference to FIGS. 3 and 4 below.

Flip-flop 11 is set/reset by the OUT command waiting for the arrival of data bit Dn and stores the clock selection signal (line 4). Here, when the signal transmitted on line 4 is at a high level, flip-flops 12 to 15 are busy in the set state, and one of the ordarts 16 is at a high level, so the clog Δ is ignored. .One way of entering Or Gate Z7'd,
Since it is at "Low" level, clock 13 is output to line 5 through AND gate I8. OU
When flip-flop 11 is reset by the 1'' instruction, flip-flops 14 and 1 are reset at the rising edge of clock B.
5 is reset. When the flip-flop 15 is reset, one of the OR gates 17 becomes "High" level and the clock B is ignored. flip flop I
When the preset number 2 becomes "Hlgh" level, the flip-flops 12 and 13 are reset by 1 of the clock A, and one of the OR gates 16 becomes "Low" level, so that the clock signal y'7^ becomes the AND gate 1B. The output will appear on line 1 and 5. flip flop 11
When the clock is set, the switching from clock A to clock B is performed in the reverse operation.

The feature of this circuit is that a high frequency block (
In this embodiment, since the clock pulses are not narrower than the 7497 width of the clock A), the operation of the MPU is guaranteed even if dynamic switching is performed. In a system with a slow clock, unless a clock selection method is provided, the IJUT command for switching will be a NO operation. Therefore, as long as the software is coded as shown in Figure 42, there is no need to change the number of loops even if the clock frequency is increased to improve performance. Add a circuit and prepare the timer program shown in the flowchart) The following effects can be obtained: -0 That is, assuming that the CPU is operating at clock A, at that clock speed. If a software timer created at the speed of clock B is executed, the logical Wait1 time cannot be secured. (If clock A is faster than clock B, the Wait time will be shorter.) Conventionally, the timer program had to be changed every time the clock changed, but with the present invention, the timer program can be changed every time the clock changes. ! If multiple clocks are separated by adding , the speed of C1'U's clock will be sped up.If the clock used in the timer is fully loaded in the selection circuit, the clock in the timer section will always be fixed. In particular, there is no need to change the program.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the operation flow of a program in which the clock speed of the timer section is fixed, and FIG. A detailed episode'#5? I - diagram showing,
FIG. 4 is a timing chart showing the operation of the embodiment of the present invention. L... Clock selection circuit, 11-15... D type flip-flop, 16.17... OR gate, 18
...and gate.

Claims (1)

[Claims] A plurality of clocks with different frequencies are input, and a clock selection circuit supplies one of the clocks to the processor unit as an operating clock according to a control signal, and a count value corresponding to a timer is set, and the clock selection circuit is assigned in advance. a memory programmed to generate the control signal by accessing a port configured to control the clock, and to switch the clock as necessary.