JPH0740213B2 - Computer system - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a computer system having a software timer.

[Technical background of the invention and its problems]

Microprocessors (MPUs) can speed up the process of development. For example Intel 16-bit MPU808
The 6 was first announced with 5MHZ (megahertz) clock, and then upgraded to 8MHZ clock. Zilog's 8-bit MPU, Z80 started with a 2MHZ version, which was also upgraded from 4MHZ to 6MHZ. In systems using these MPUs, it is customary to raise the clock frequency according to the performance of the MPU to improve the system performance.

The only problem in this case is the software timer routine. That is, when waiting for a certain period of time (for example, when securing the settling time of the floppy disk drive), the number of loops must be 1 to 2 depending on whether the MPU clock is 4 MHz or 8 MHz. If the number of loops is set assuming 8 MHz, the wait time will be doubled at 4 MHz.
Therefore, it is necessary to change the number of loops each time the frequency changes, which is a burden on the programmer.

[Object of the Invention]

The present invention has been made based on the above circumstances, and an object of the present invention is to provide a computer system in which the load on the programmer is reduced by dynamically changing the clock speed of the software timer portion.

[Outline of Invention]

In order to achieve the above object, the present invention has a configuration in which any one of a plurality of types of clocks input by further adding a clock selection circuit to the conventional components of this type computer system is supplied to the processor unit. At the same time, after setting the count value, a program is prepared for accessing the port to which the selection circuit is assigned, switching the clock to the one for the timer, and switching to the original clock after the timer ends. According to the program, the clock speed of the software timer is dynamically fixed, and the work of recreating the software timer at the clock speed is unnecessary.

This eliminates the need to change the program and reduces the burden on the software programmer.

Example of Invention

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
In the figure, reference numeral 1 is a clock switching circuit, and clocks A and B having different frequencies are supplied via lines 2 and 3, respectively. The signal supplied via the line 3 is a control signal, and one of the clocks A and B is selectively output via the line 5.

FIG. 2 shows an operation flow of a program in which the clock speed of the timer part is fixed. The program is the clock selection circuit shown in FIG. 1 after setting the count.
The port to which 1 is assigned is accessed, the clock is switched to that for the timer, and the process of switching to the original clock after the timer is completed is performed. Details will be described later.

FIG. 3 is a diagram showing a specific circuit configuration of the clock selection circuit 1 shown in FIG. The clock selection circuit 1 includes five D timer flip-flops 11, 12, 13, 14, 15 and two OR gates 16, 17 and one AND gate 18. In the figure, the same symbols or numbers as the symbols or numbers given in FIG. 1 are the same as those in FIG. Further, Dn indicates a data bit, and OUT indicates a signal which arrives by the OUT instruction.

FIG. 4 is a timing chart showing the operation of the embodiment of the present invention. In the figure, blocks or lines with the same numbers as those in FIG. 3 are the same as those in FIG.

Hereinafter, the operation of the embodiment of the present invention will be described in detail. First, a schematic operation will be described with reference to FIGS. 1 and 2. The clock A and the clock B are input to the clock selection circuit 1 via lines 2 and 3, respectively. The clock A and the clock B are clocks having different frequencies. Normally, the CPU is operating with the clock signal output (line 5) of either clock A or clock B. To switch to the other clock, a control signal (line 4) is assigned to a certain port address, and that port is accessed by a program to invert the control signal.
That is, after a count number is set in a part (wait in the flowchart shown in FIG. 2) corresponding to a timer (loop) in a certain program, the port to which the clock selection circuit 1 shown in FIG. The clock is fixed during the actual loop by switching to the logical clock at the time of design as necessary. When the loop is finished, access the port again and
Switch to the CPU clock and perform the subsequent processing.

The clock switching operation will be described in detail below with reference to FIGS. 3 and 4.

The flip-flop 11 is set / reset by the UT instruction waiting for the arrival of the data bit Dn, and stores the clock selection signal (line 4). Here, when the signal propagating on the line 4 is at the “High” level, the flip-flops 12 to 1
Clock 5 is ignored because clock 5 is in the set state and one of the OR gates 16 is at the "High" level. Since one input of the OR gate 17 is at "Low" level, the clock
13 is output to the line 5 through the AND gate 18. When the flip-flop 11 is reset by the UT instruction, the flip-flops 14 and 15 are turned on at the rising edge of the clock B.
Is reset. When the flip-flop 15 is reset, one of the OR gates 17 becomes "High" level and the clock B is ignored. When the preset of the flip-flop 12 becomes "High" level, the flip-flops 12 and 13 are reset at the rising edge of the clock A, and one of the OR gates 16 becomes "Low" level, so that the clock A is output to the line 5 through the AND gate 18. Will be done. When the flip-flop 11 is set, the clock A is switched to the clock B by the opposite operation.

The characteristic of this circuit is that the pulse width is not narrower than the pulse width of the high-frequency clock (clock A in this embodiment) at the time of switching, so that even if switching is performed dynamically.
The operation of the MPU is guaranteed. In a system with a slow clock, the UT instruction for switching is a NO operation unless the clock selection circuit 1 is provided. Therefore, if the software is coded as shown in FIG. 2, it is not necessary to change the number of loops even if the clock frequency is increased to improve the performance.

〔The invention's effect〕

As described above, adding the clock selection circuit described above,
In addition, the following effects can be obtained by preparing the program of the timer unit shown in the flowchart. That is, assuming that the CPU is operating at the clock A and executing the software timer made at the speed of the clock B at that clock speed, the logical Wait time cannot be secured. (If the clock A is faster than the clock B, the Wait time becomes shorter.) Conventionally, the program had to be changed in the timer each time the clock changed, but a plurality of selection circuits are added by adding a selection circuit as in the present invention. Even if the clock is input and the CPU clock is speeded up, if the clock used for the timer is input to the selection circuit, the clock of the timer section will always be fixed, so the program change It is unnecessary.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an operation flow of a program in which the clock speed of a timer portion is fixed, and FIG. 3 is a diagram showing the clock selection circuit shown in FIG. FIG. 4 is a diagram showing a detailed circuit configuration, and FIG. 4 is a timing chart showing the operation of the embodiment of the present invention. 1 ... Clock selection circuit, 11 to 15 ... D type flip-flop, 16, 17 ... OR gate, 18 ... AND gate.

Claims (1)

[Claims] 1. In a computer system for supplying an operating clock of a predetermined frequency to a processor unit and operating various programs based on this clock, a first clock for operating a normal program and a software timer loop are provided. The second clock to be operated is input and a clock selection circuit that outputs one of the clocks to the processor unit according to a predetermined signal, and the clock supplied to the processor unit before the software timer loop operation is the first clock. From the second clock to the second clock, and a second signal that switches the clock output from the clock selection circuit from the second clock to the first clock after the end of the software timer loop. And a means for outputting a signal. Computer systems that.