JPH05342142A - Direct memory access control system - Google Patents

Abstract

PURPOSE:To execute an optimal distribution of buses from the viewpoint of a system side and a user side, and to improve the processing capacity of the system by setting a timer value as an initial value from the outside at every channel, comparing count timer values, and setting the channel having the smallest value as the highest priority. CONSTITUTION:In CH0-CH3, decrementers 103-106 are provided by one each, and a user sets a timer value as an instruction from a CPU side. When the control right of a bus cannot be obtained yet although a DMA operation request signal is active, a value of the decrementers 103-106 is subjected to decrement. This value is latched by a temporary register 108, whenever a SAMPLE signal 121 or a DMA operation executing request input signal to one channel becomes active for a certain prescribed period, and compared with a timer value of the adjacent channel by a comparator 112. Subsequently, in the end, a channel number whose timer value is the smallest at that time point is outputted as an SEL-CH 118, and this channel is selected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct memory access control system having a plurality of channels, and more particularly to a single channel selection system when a DMA operation execution request is issued from a plurality of channels.

[0002]

2. Description of the Related Art Due to dissatisfaction with the processing capacity of a system, there is an increasing demand for speeding up of the microprocessor that is the core of the system. However, at present, in order to speed up not only the microprocessor but also the entire system, the peripheral chip of the microprocessor is used to achieve even higher speeds, and cache memory and direct memory access control are examples. ..

In particular, in direct memory access control, an input / output device (hereinafter referred to as I / O) or a main storage device is generally orders of magnitude slower than the speed of individual calculations in a central processing unit (hereinafter referred to as CPU). Direct memory access controller (hereinafter DMAC)
The controller called "()" controls and manages buses such as an address bus and a data bus in place of the CPU. Here, the DMAC becomes the bus master.

Therefore, the CPU does not have to perform the above-mentioned processing in which the access time is extremely slow, and the burden on the CPU can be considerably reduced only by leaving the processing to the DMAC.

Since a plurality of I / Os such as a floppy disk controller, a hard disk controller, a communication controller and the like are generally connected to the CPU, the DMAC is also provided with a plurality of I / Os.
At this time, if there are execution requests from the multiple I / Os to the DMAC, I / O may be changed depending on which channel is selected and executed.
It determines the processing capacity of the entire system including O.

Generally, there are the following two types of channel selection methods. The first method of channel selection from multiple execution requests is a method called fixed priority order. This method is to give priority to each channel and fix the order. FIG. 3 shows an example of the state of the selected channel when each DMA operation is requested.

Now, DRQ0 and DR are arranged in descending order of priority.
Q1, DRQ2, and DRQ3. First, when a DMA operation execution request is issued to the channel corresponding to DRQ1,
At that time, the bus is controlled by the CPU,
The control of the bus is transferred to DRQ1 and the DMA operation requested by the channel is performed.

Next, during execution of the DRQ1 DMA operation, D
When there is a DMA operation execution request for DRQ0 having a higher priority than RQ1, the DMA operation for DRQ1 is once held and the DMA operation for DRQ0 is executed. DR
When the DMA operation of Q0 ends, the D held
The operation of RQ1 is started again. After that, this time DRQ1
Even if there is a request to execute the DMA operation of DRQ3 having a lower priority, the request to execute the DMA operation of DRQ3 having a lower priority is ignored and the DMA operation of DRQ1 is continued. Therefore, the DMA operation of DRQ3 will be executed after the end of DRQ1.

The above description is for three channels, but the same operation is performed even if the number of channels exceeds three. This method can simplify the hardware because the priority is already fixed for each channel in the hardware.

However, the processing capacity of the entire system is determined by what I / O device is connected to each channel whose priority is fixed. Further, if the priority order is not so particular, it is difficult to set the optimum priority order for the processing capability of the entire system if the priority order is forced to be connected to each channel.

FIG. 4 shows an example of the priority selection circuit as a priority encoder. Reference numeral 401 is a DMA transfer request signal (4 bits) for each channel, 402 is a selected channel number in fixed priority order, and 403 is a priority encoder.

The second method of channel selection from a plurality of execution requests is a method called rotation priority order. FIG. 5 shows an example of how channels are selected by this method. Consider the case of a total of four channels as in the fixed priority order. First, 4
DRQ for any one of the channels
When a request (here, DRQ1) is made, the DMA operation of that channel is executed.

In the rotation priority order, the priority order of the channel in which the DMA operation is being executed is the lowest priority order immediately after the completion of the DMA operation or after a certain period of time. Therefore, there is a DMA execution operation request of DRQ3 while the DMA operation of DRQ1 is being executed. , DRQ
The DMA operation of 1 is held and the DMA operation of DRQ3 is started. Thereafter, this priority order selection method is used.

According to the rotation priority order, it is possible to prevent a specific channel from monopolizing the bus, so that an average waiting time can be expected for each I / O device.

FIG. 6 shows the easiest method as a circuit for realizing the rotation priority order. 601 is a decoder, 602 is a selector, 603 is a priority encoder with channel 0 as the lowest priority, 604 is a priority encoder with channel 1 as the lowest priority, and 605 is a priority encoder with channel 2 as the lowest priority, Reference numeral 606 is a priority encoder having channel 3 as the lowest priority, 607 is a DMA operation request signal, 608 is the last selected channel number, and 609 is the channel number selected by the rotation priority order.

Priority encoders 603, 60
The output results of 4, 605 and 606 are selected by the selector 602, and the encoder based on the rotation priority order is selected by the last selected channel number 608.

In addition, a method in which the above two types of channel selection methods are mixed is also used.

[0018]

As described above, according to the conventional plurality of DMA operation request input selection methods, the I to be connected is connected.
Unless the connection of I / O devices is changed internally, the optimal and effective I / O device allocation for the system cannot be expected.

Therefore, the priority order of the plurality of I / O devices to be connected does not change so much, but the priority order is forcibly set. Therefore, unless the connection is changed, the channel selection method set to the end is selected.

It is an object of the present invention to provide a direct memory access control system for optimally allocating buses as seen from the system side and the user side and increasing the processing capacity of the system.

[0021]

In order to achieve the above object, a direct memory access control system according to the present invention is a direct memory access control system having a plurality of DMA operation request inputs, in which a timer value is externally assigned to each channel. It has a means for designating, a holding circuit for holding a timer value for each channel, a circuit for counting for each channel between the DMA operation request and approval, and means for dynamically changing the priority order. , A timer value is externally set as an initial value for each channel, a countdown is performed while the DMA operation request signal is active and the DMA operation approval signal is inactive for each channel, and the count timer values are compared to determine the minimum value. The channel with a value is the highest priority.

[0022]

A timer value is externally set as an initial value for each channel, a countdown is performed while the DMA operation request signal is active and the DMA operation approval signal is inactive for each channel, and the count timer values are compared. The channel with the smallest value has the highest priority.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing an apparatus for carrying out a method for selecting a channel from a total of 4 channels using the present invention.

In FIG. 1, 101 is a timing generation block, 102 is an output of the timing generation block, and 10 is a timing generation block.
3 is a channel 0 decrementer, 104 is a channel 1 decrementer, 105 is a channel 2 decrementer, 1
Reference numeral 06 is a channel 3 decrementer, and 107 is an n-bit timer value bus. Further, 108 is a temporary register, 109 is an enable signal of the register 108, 11
0 is a 2-input AND gate, 111 is a 2-input OR gate,
112 is a comparator, 113 is an n-bit timer value bus,
114 is the output result of the comparator, and 115 is the clock synchronization e.
The enable signal 116 is a selector.

Further, 117 is a decoder, 118 is a selected channel number, 119 is an n-bit timer value output of the selector, 120 is a two-phase clock, 121 is a sampling signal for a certain period, and 122 is a DMA operation request. , 123 is a two-phase clock (a pair with 120).

In the figure, in this embodiment, there is no fixed channel priority for each channel, and CH0, CH
Decrementors 103 and 1 for CH1, CH2 and CH3
04, 105, 106 are provided, and the user sets a timer value in the decrementer of the channel to be used as an instruction from the CPU side.

Here, the control signal INIT-S
Initialization is performed with the initial register value REG-INIT by TB. This is the timing of the timing generation circuit 101 (for example, a frequency divider of 2 or 4 of the clock signal) for each channel generated by the system clock, and
When the A operation request signal is active but the bus control right is not yet obtained (the DMA operation request acknowledge signal is inactive), the decrementers 103, 104, 105, 1
The value of 06 is decremented. This value is a two-phase clock φ1 clock 120, φ2 clock 1 every time the SAMPLE signal 121 or the DMA operation execution request input signal for any channel becomes active for a certain period.
In synchronization with 23, the timer value (n bits, n is a natural number) is latched in the temporary register 108 and compared with the timer value of the adjacent channel by the comparator 115.

Finally, the channel number with the smallest timer value at that time is output as SEL-CH 118, and this channel is selected.

In FIG. 1, two first-stage comparators 11 are provided.
The decoder 117 decodes the desired channel number 118 from the output results of the second and second stage comparators 112.

According to this embodiment, the user can determine the priority of each channel arbitrarily to some extent according to the scene. In addition, since the priority of the channels approaching the time-out time can be raised, it is possible to optimally allocate the I / O devices of the bus to the system.

(Second Embodiment) FIG. 2 is a block diagram showing a second embodiment of the present invention. In FIG. 2, 201 is a timing generation circuit (such as a frequency divider), 202 is an enable signal of the timing generation circuit, and 203 is a DM of channel 0.
ARQ signal latch register, 204 is a channel 1 decrementer, 205 is a channel 2 decrementer, 206
Is a channel 3 decrementer, 207 is a timer value bus for each channel, 208 is a signal for DMARQ0, and 209 is a temporary register for channel 0. Further, 210 is a temporary register of channels 1 to 3, 211 is an n-bit timer value bus, 212 is a synchronization signal of the temporary register, 213 is a 2-input AND gate, and 214 is a 2-input O.
It is an R gate. Further, 215 is a two-phase clock, 216 is a sampling signal for a certain period, 217 is a signal indicating that there is a DMA operation request, 218 is a timer value minimum channel selection block, 219 is an output of the DMARQ0 temporary register, and 220 is a block 218. Output signal, 221 is a decoder, and 222 is a selected channel number according to the second embodiment.

In the present embodiment, there is one fixed top priority channel (here, CH0) out of a total of four channels.

The configuration is the same as that of the first embodiment except for the fixed top priority channel portion. The smallest channel among the timer values set in the decrementers 204 to 206 of CH1, CH2 and CH3 is selected from the timer value minimum channel output block 218 by the same procedure as in the first embodiment.
The channel number is output as 0.

However, since the fixed highest priority channel exists in the present embodiment, the channel of the selected output signal 220 can operate the DMA only when there is no DMA operation request of the highest priority channel CH0. This is the decoder 221
D indicating whether the CH0 DMA operation request is active
MARQ0 and timer value minimum channel output block 218
Is decoded from the output signal 220.

According to this embodiment, it becomes unnecessary for the user to substitute a timer value for the decrementer of CH0 for an I / O device having an extremely high frequency of use and a high priority.

[0037]

As described above, by using the present invention, the user can specify the access priority of the already connected I / O devices, and the priority can be dynamically changed according to the processing content. Therefore, the bus allocation of I / O devices that is optimum for the system, that is, the most effective direct memory access control can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration according to a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration according to a second exemplary embodiment of the present invention.

FIG. 3 is a diagram showing a state of each channel when there is a DMA operation request from each channel by a channel selection method called fixed priority order in the prior art.

FIG. 4 is a diagram illustrating a priority encoder in which fixed priority channels are selected.

FIG. 5 is a diagram showing how channels are selected by a method called rotation priority order in the prior art.

FIG. 6 is a block diagram of selecting an output of a priority encoder corresponding to each channel according to a channel whose rotation priority is selected last.

[Explanation of symbols]

 101 timing generation block 102 output of timing generation block 103 decrementer of channel 0 104 decrementer of channel 1 105 decrementer of channel 2 106 decrementer of channel 3 107 n-bit timer value bus 108 temporary register 109 enable signal of register 108 110 2 input AND gate 111 2-input OR gate 112 Comparator 113 n-bit timer value bus 114 Output result of comparator 115 Clock enable signal 116 Selector 117 Decoder 118 Selected channel number 119 n-bit timer value output of selector 120 2 Phase clock 121 Sampling signal for a certain period of time 122 Signal telling that there was a DMA operation request 123 Two-phase clock (120 201) Timing generation circuit (such as a frequency divider) 202 Enabled signal of timing generation circuit 203 DMARQ signal latch register of channel 0 204 Decrementer of channel 1 205 Decrementor of channel 2 206 Decrementer of channel 3 207 For timer value of each channel Bus 208 DMARQ0 signal 209 Channel 0 temporary register 210 Channels 1 to 3 temporary register 211 n-bit timer value bus 212 Temporary register synchronization signal 213 2-input AND gate 214 2-input OR gate 215 2-phase clock 216 Certain period Sampling signal 217 Signal indicating that there was a DMA operation request 218 Timer value minimum channel selection block 219 DMARQ0 Temporary register output Output 220 Output signal of block 218 221 Decoder 222 Selected channel number according to the second embodiment

Claims (1)

[Claims] 1. A direct memory access control system having a plurality of DMA operation request inputs, means for externally designating a timer value for each channel, a holding circuit for holding a timer value for each channel, and each channel. It has a circuit for counting each DMA operation request from the time of approval and a means for dynamically changing the priority order, and sets a timer value from the outside as an initial value for each channel to perform a DMA operation for each channel. A direct memory access control method, wherein a countdown is performed while the request signal is active and the DMA operation approval signal is inactive, the count timer values are compared, and the channel having the smallest value is set to the highest priority.