JPS61141064A - Electronic circuit - Google Patents

Abstract

PURPOSE:To set the start timing of data transfer in terms of a program by installing a data transfer standby means between a memory means and an arithmetic control means. CONSTITUTION:WNDATA from a microprocessor is given to a select signal generator circuit 9 to generate select signals SELSG1-SELSGn, which are input ted to a data selector part 8. Then, when the microprocessor makes a memory read start signal RD active, a weight signal generator circuit 6 makes a WAIT12 active and informs the microprocessor that it should make a WAIT12 active and weight it. A delay circuit 7 inputs the WAIT12 and CLOCK to gener ate timings Z2-Zm delayed by one clock from the WAIT12. According to the logical value of the signal inputted to select input terminals S1-Sn, the data selector 8 selects any of signals 0, Z2-Zm inputted to input terminals D1-Dm to output it to the weight signal generator circuit 6, and resets said circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field 1 The present invention relates to an electronic circuit having an arithmetic control means such as a microprocessor, and particularly to an electronic circuit that synchronizes data input and output thereof.

L Prior Art j In recent years, the processing speed of arithmetic control devices such as microprocessors has improved, so when @wing control devices read programs and data from memory or input/output ports, data transfer and data transfer are performed in the machine cycle of the microprocessor. In some cases, it may be necessary to insert a wait cycle to achieve synchronization.

Particularly in the read operation of a microprocessor, the fastest access time is generally required when reading a program from memory. A circuit inserted into the processor is used.

Furthermore, since input/output ports generally have slow access times, when a microprocessor accesses an input/output port, one wait cycle is automatically inserted into the microprocessor.

However, these days, when there are low-speed and high-speed versions of microprocessors and memory with the same model name, the following problems occur. For example, in the early days, if you connect a low-speed version of memory to a low-speed microprocessor, , no wait cycles are required even when the microprocessor performs read operations from memory. However, when specifications change, such as replacing a high-speed microprocessor with a higher system clock frequency, two wait cycles may be required when reading a program, and one wait cycle when reading memory other than program reading. be. Also, on the contrary, it uses a slower version of memory,
Initially, 2 wait cycles were inserted when reading a program, and 1 wait cycle was inserted when reading memory other than program reading, but by replacing it with a high-speed version of memory, reading can be performed by inserting only 1 wait cycle when reading a program. Even if this could be done, in the prior art, the wait cycle insertion circuit had to be redesigned each time, or the microprocessor had to be used with unnecessary wait cycles inserted.

The former is uneconomical in terms of cost, and the latter is not a good idea in terms of effective use of the microprocessor.

The above-mentioned problem occurs not only in microprocessors but also in so-called minicomputers, even when the used elements are changed from TTL to 0MO3 or from TTL to touch key TTL.

The present invention has been made in view of the above points, and its purpose is to provide an electronic circuit that can programmatically set the start timing of data transfer between a storage means and a playlist control means or an input/output control means. It is there to provide.

Embodiments Embodiments to which the present invention is applied will be described below with reference to the drawings.

Figure 1 is a circuit block diagram of the embodiment.
7 is a wait signal generation circuit, 7 is a delay circuit, 8 is a data selector, and 9 is a select signal generation circuit. Also, RO is the microprocessor memory read start signal, CLOCK.
is the microprocessor system clock, WNDATA
are the microprocessor's data bus, address bus, and other control signals (e.g., REQ, l
0RQ, etc.), etc.).

The operation of the embodiment will be explained. First, the microprocessor sets and outputs an appropriate WNDATA to set an excessive wait time. The select signal generation circuit 9 is WNDA
0 Next, when the microprocessor makes RDI active, the wait signal generation circuit 6 causes the microprocessor to select WA.
Make ITI 2 active and notify that it should wait. When WAITI2 becomes active, the delay circuit 7 starts operating. The delay circuit 7 inputs WAITI 2 and CLOCK and generates timings 22 to Zm each delayed by l clocks from WAITI 2.

-10,000, data selector 8 is select input terminal 51~Sn
According to the logic value of the signal input to the input terminal, ,D2~
One of the signals 0 and Z2 to Zm (delay circuit output) input to D11 is selected. Therefore, the edge signal RES 11 resets the wait signal generation circuit 6 after a selected predetermined time. Wait signal generation circuit 6
When reset, signal WAITI 2 becomes 1nacti
Become ve. IIIAITI 2 is 1nactive
If so, the microprocessor sets RD to 1nactive. The delay circuit 7 knows that the microprocessor has finished the read operation when RD becomes 1nactive, and resets itself.

In this way, any wait cycle can be set using WNDATA, which can be programmed and output from the microprocessor.

FIG. 2(a) is a circuit diagram in which the above-described embodiment is applied to a system using, for example, a microprocessor Z80 manufactured by Zi Log, Inc. of the United States. Moreover, FIG. 3(a) shows the above Z
FIG. 3(b) shows the bus timing of the signal line terminals of the 80 microprocessor.

As is well known, in the 280 microprocessor system, the WAI? There is a cycle. That is, when -AIT/ is returned in response to the control signal RD/ for reading/writing to the memory (hereinafter, / after the signal name indicates negative logic) or WR/ or l0RQ/ for the input/output device, za
Within o, t1→t2'.

→' The timing of T 3 changes to t1 → t2 → tw, causing the internal state to wait temporarily.

! $2 In the embodiment shown in Figure (a), from Z80 to RD/
When receiving the signal, the output WAIT/12 of the flip/flop (hereinafter referred to as FF) becomes variable in accordance with the logical values of the signals 5ELSG+ and 5ELSG2.

First of all! $2 The logic element in Figure (a) will be explained. 1
-4 are Edge Trigger D type FFs, each FF
Inside, D is a data input terminal, GK is a clock input, and Q is an output. PR/ is a preset input terminal and becomes active when the logic is O'. 5 is a data selector, and the logic of select inputs sl and s2 is Figure 4 (a
), input terminals A and B.

Either C or D is selected and output to output terminal Y.

Signals 5ELSG+ and 5ELSG2 are connected to the latched output ports of the Z80 microprocessor or the fifth
This is a signal from the select signal generation circuit 9 shown in the figure, and the values of the signals 5ELSG1 and 5ELSG2 can be changed programmatically.

The broken line 6 indicates WAIT/corresponding to 6 in FIG.
The signal generation section, also indicated by the broken line 7, is the delay circuit section.
A broken line 8 is a data selector section.

According to the circuit in Figure 2(a), 'dAIT/12 is RD
It becomes active when the logical value of / becomes 1-0,
The interval is until O is input to the PR/input terminal of FFI. The PR/input of FF1 is the output terminal Y of the data selector 5, and Y has 0. FF2 output, FF3 output.

One of the FF4 outputs is output. As can be easily seen from Figure 2 (a), the output of the FFI is sequentially FF2→FF3.
→Since it is input to FF4, the outputs of FF2 to FF3 are each delayed by ICLDGK time. Therefore signal 5EL
The WAIT/ interval is 0.1, 2, or 3 CLOCK times depending on the values of SG and 5ELSG2.

In - Yu 10's role is to F when RD/ becomes 0-1.
This is to reset F2 to FF3.

In FIG. 2(b), as an example, when the signals 5ELSGI and 5ELSG2 are both logic values "1", WAIT/12 is 3.
It shows how it becomes active during the CLOCK time. The data selector 5 receives the signal from the input terminal, that is, the FF
4 output is selected. In other words, WAIT/1
2 is active until FF4 is reset.

This will be explained with reference to the timing chart of FIG. 2(b). Since RD/ becomes logic ``0'' with a little delay from the falling edge of t1 cycle, the output of FFI becomes logic ``0'' at the rising edge of t2 cycle. Therefore, WAI
T/l 2 is logic °°0” at the rising edge of t2 cycle
becomes.

When microprocessor Z80 learns that WAIT/l 2 is logic a+07# at the falling edge of cycle t2, the next cycle becomes wait cycle t111.

Next, at the rise of wait cycle tw1, the output of FFI is shifted to FF2. Even at the falling edge of wait cycle tWl, WAIT/l2 is at logic "0°", so 2
The next cycle after 80 is also a wait cycle tw2.0
Next, at the rise of wait cycle tl12, the output of FF2 is shifted to FF3. %IAI even at the falling edge of wait cycle t112? Since /12 is logic "0", the next cycle will also be wait cycle tl13. Next, at the rise of wait cycle tl13, the output of FF3 is shifted to FF4. Signals 5ELSG and 5ELS
Since G2 remains at logic -1''', the output RES l l of the data selector 5 is the output of FF4. Therefore,
When the output of FF4 becomes logic “o”, RES l 1
This resets the FFI so that the output becomes logic "IIT" and WAIT/l2 becomes logic "IIT". At the falling edge of wait cycle Lj13, WAI↑/12
Since the logic is "1", the primary cycle is the t3 cycle. Z80 after a little delay from the falling edge of t3 cycle
When RD/ becomes logic "l", the output of inverting circuit lO becomes logic "o", and the preset input terminals PR/ of FF2, 3, 4 also become logic "O'', as shown in FIG.
As shown in the timing chart of b), FF2, F
F3.

FF4 becomes logic "1".

As described above, when the circuit of FIG. 2(a) is used in the Z80 system, three wait cycles are inserted if the Z80's latched output signals 5ELSG+ and 5ELSGz are at logic -1''.

Similarly, latched S output signals 5ELSG+ and 5ELS
Setting G2 to logic "0" or "1'°" means 2 wait cycles, setting it to logic "1" or "O" means 1 wait cycle, and setting it to logic "0" or "0'' means no wait cycle. Become.

As explained above, if the circuit of FIG. 2(a) is used,
When reading Z80, insertion of O wait cycles to 3 wait cycles can be selected programmatically.

In FIG. 2 (&), the read start signal RD/ is applied to the write start signal WD/or the program read signal Ml (third
If you replace it with figure (a)), even when reading a program, O
Insertion of 3 wait cycles can now be selected from the wait cycles by program.

Also, the circuit in Fig. 2(a) is 5ELSG+, 5ELSG
2 was input directly from the Z80, but 5ELSGI and 5EL from the select signal generation circuit 9 in FIG.
If SG2 is input, the application range of the weight signal will be widened. Therefore, the select signal generation circuit 9 will be explained below.

FIG. 5 is a block diagram of an example of the select signal generation circuit 9 when the embodiment shown in FIG. 1 is incorporated into a 280 system. Input signals in FIG. (See Figure 883(a)) In Figure 0, DCOD20.

21 is an address decoding circuit, and address bus A1
It is determined whether or not 5 to AO are within a specific address range defined by each address decoding circuit, and 1 or 0 is output. That is, the DCOD 20 makes a determination regarding a specific address range of the main memory.

However, each of the 000 ports 21 determines the range of port addresses of the 10 ports. LAT 22 and 23 are latch circuits, and the wait time is L
It is determined by the logical values of data buses D7-Do latched by AT22.23. The FORT signal is a WAIT signal that is set according to the difference in data transfer speed of each input/output port.
/ l 2 A port output signal of 8255 manufactured by Intel Corporation in the United States can be considered as an example. TRB 29, 30, and 31 are well-known tri-state buffers whose outputs change to 0.1 or high impedance depending on their control signals and inputs.

The output of each TRB will be explained in turn.

In Figure 5, when reading the program, DCOD20
and Ml (gate 26), LAT22
The content of is the select signal 5ELSGl from TRB29.
5ELSGn is outputted to the selector input of the data selector 8 in FIG. 2(a).

When reading memory other than when reading a program, M
AND output (gate) of inverted signals of EMREQ and Ml 25
) and the output of the DCOD 20 (gate 27), the contents of the LAT 23 are output from the TRB 30 as select signals 5ELSG+ to 5ELSGn to the select input of the data selector 8 in FIG. 2(a).

When reading from the input/output port, the logic a (gate 28) of the input/output boat request signal l0RQ and the output of DCOD21 causes the signal PORT sent from a circuit not shown in FIG. The contents of TRB 31 select signal 5ELSG+~5ELS
It is output as Go to the select input of the data selector 8.

As you can see from the above explanation, if you use the circuit shown in Figure 5,
When reading a program, when reading a memory other than when reading a program, and when reading an input/output port, the selection is made independently to the select input of the data selector 8 in FIG. 2(a), and only in a specific address range for each. Signals sgt, sat''5ELSGn can be output.

In this way, a wait cycle of any length can be programmatically inserted into a microprocessor system having a wait cycle, limited to the Z80 microprocessor, by using a signal generating circuit such as the embodiment shown in FIG.

Further, according to this embodiment, when reading a program, when reading a memory other than when reading a program, and when reading an input/output board, the number of wait cycles for each read is programmed by limiting the address to a specific range for each. It can be set variably by

Therefore, even if you mix memories with different access times or mix input/output ports with different access times and connect them to a microprocessor, you can easily operate the system without reducing the efficiency of the microprocessor. Even if the memory access time changes due to a change in the specifications, or if the microprocessor is replaced with a faster version and the system clock becomes higher, the program can flexibly handle the situation.

Effect E" As explained above, according to the electronic circuit of the present invention, the start timing of data transfer can be varied in various ways programmatically.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment according to the present invention, and FIG. 2 (a
) is the 1st r1! Partial detail diagram of the embodiment of J, FIG. 2(b)
2(a) is a timing chart of the embodiment of FIG. 2(a), and FIG. 3(a) is a diagram showing input/output signals of a microprocessor used in a part of the embodiment. FIG. 3(b) is a path timing diagram of the microprocessor of FIG. 3(&). 4 (IiL) and (b) are diagrams showing the truth values of the data selector 5, and FIG. 5 is a detailed circuit diagram of the select signal generation circuit 9. In the figure, 1, 2, 3.4... FF', 5... data selector, 6... wait signal generation circuit, 7... delay circuit, 8... data selector section, 9...・Select signal generation circuit, 20.21...address decoding circuit C
DC0D), 22, 23...Latch circuit (LAT
), 29.30.31...tristate buffer (
TRB') Figure 2 (b) Figure 3 (a). Medium 5V GND

Claims (2)

[Claims] (1) Arithmetic control means that performs logical operation control, storage means that stores data or programs, and first data that programmatically sets the start timing of data transfer between the storage means and the arithmetic control means. An electronic circuit having transfer standby means. (2) It further includes an input/output control means and a second data transfer standby means, and the second data transfer standby means programmatically controls the start timing of data transfer between the storage means and the input/output control means. An electronic circuit according to claim 1, characterized in that the electronic circuit is set to .