GB1385890A - Arrangement for correcting of seconds indication of a timepiece - Google Patents

Abstract

1385890 Electronic timepieces SOC SUISSE POUR L'INDUSTRIE HORLOGERE MANAGEMENT SERVICES S A 24 Nov 1972 [16 Dec 1971] 58470/71 Heading G3T Relates to a seconds setting/correcting arrangement in an electronic timepiece comprising a crystal controlled oscillator followed by a frequency divider counter chain including stages 14, 15 (Fig. 1) the output of which is applied to a time display via a bi-stable flip-flop CM. The display may comprise hands driven by a stepping motor M or alternatively be of liquid crystal or solid state type. Each time a switch P 1 is depressed one second is added and each time P2 is depressed one second is blocked from the time display. Depression of P 1 results in a reset output Q from a bi-stable storage device 16 which causes subsequently an additional setting of flip-flop CM and therefore an additional pulse from the output Q of CM and an additional advance of 1 second in the display. The pulse duration of the output pulses from CM is determined by reset pulses at R derived for example from the eighth stage of the divider, and their timing and frequency by set inputs S 1 S 2 . Input S 2 will normally have no effect so long as P 1 is not depressed to set storage device 16. When P 2 is depressed a bi-stable storage device 17 is set so that its output Q = 1. Thus a transistor T 1 will conduct bringing a point B to O. At the moment the next input S 1 arrives at CM the output Q CM changes to 1 and Q CM changes to O. However B remains at O since change of Q CM from 1 to 0 will not change the state of device 17 and a pulse from CM output Q is thus suppressed. The next reset pulse R to CM returns it to its reset state where Q CM = 1 and storage device 17 is thereby reset. T 1 will therefore be cut-off until P 2 is again depressed, only one drive pulse having been eliminated.