JPS57187753A - Status recording system for information processing device - Google Patents

Status recording system for information processing device

Info

Publication number
JPS57187753A
JPS57187753A JP56072603A JP7260381A JPS57187753A JP S57187753 A JPS57187753 A JP S57187753A JP 56072603 A JP56072603 A JP 56072603A JP 7260381 A JP7260381 A JP 7260381A JP S57187753 A JPS57187753 A JP S57187753A
Authority
JP
Japan
Prior art keywords
output
status
address
input
main storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56072603A
Other languages
Japanese (ja)
Inventor
Hiroshi Kawahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56072603A priority Critical patent/JPS57187753A/en
Publication of JPS57187753A publication Critical patent/JPS57187753A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment

Abstract

PURPOSE:To perform the tracing of input/output operations, the logging of errors, etc. efficiently, by connecting a status recording device between a main storage device and a system bus when a predetermined status is generated. CONSTITUTION:When an error occurs, a central processing device issues a reading command for the response status to an input/output controller for the purpose of receiving the response of the input/output controller to obtain its contents. At this time, the response status is transmitted again on a data line 19, and the output of a condition setting/discriminating circuit 13 is transmitted to an address selector 12, and then, the signal of an address line 20 of a system bus 6 is suppressed, and the output of an address register 11 is outputted as an address of a main storage device. Thus, contents of the data line 19 (the status of an input/output device) are written in a prescribed address of the main storage device.
JP56072603A 1981-05-14 1981-05-14 Status recording system for information processing device Pending JPS57187753A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56072603A JPS57187753A (en) 1981-05-14 1981-05-14 Status recording system for information processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56072603A JPS57187753A (en) 1981-05-14 1981-05-14 Status recording system for information processing device

Publications (1)

Publication Number Publication Date
JPS57187753A true JPS57187753A (en) 1982-11-18

Family

ID=13494131

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56072603A Pending JPS57187753A (en) 1981-05-14 1981-05-14 Status recording system for information processing device

Country Status (1)

Country Link
JP (1) JPS57187753A (en)

Similar Documents

Publication Publication Date Title
US4156932A (en) Programmable communications controller
GB1434827A (en) Data processing system
JPS57117027A (en) Signal sending and receiving circuit
JPS57187753A (en) Status recording system for information processing device
JPS57167200A (en) Memory backup circuit
JPS6423354A (en) Duplex buffer memory control system
SU1312591A1 (en) Interface for linking electronic computer with peripheral unit
JPS57183700A (en) Information processor
JPS5736327A (en) Bas check system
JPS57135496A (en) P-rom compensating circuit
JPS56105546A (en) Memory mapping circuit
JPS5727342A (en) Error checking system for error detecting correcting circuit
JPS5730454A (en) Terminal equipment
JPS5547522A (en) Control system of input and output device
JPS5748125A (en) Channel device
JPS57101959A (en) Main storage device
JPS57168318A (en) Data transmitting device
JPH01236389A (en) Memory card
JPS57174724A (en) Error countermeasure controlling system for transfer data between computer devices
JPS5733496A (en) Data processor
JPS57137917A (en) Error information transfer system
JPS5748149A (en) Memory device
JPS5557962A (en) Error detection system
JPS6421657A (en) Priority setting system
JPS57117199A (en) Memory device possible for remote supervisory