JPS5731023A - Interface system in device - Google Patents
Interface system in deviceInfo
- Publication number
- JPS5731023A JPS5731023A JP10693480A JP10693480A JPS5731023A JP S5731023 A JPS5731023 A JP S5731023A JP 10693480 A JP10693480 A JP 10693480A JP 10693480 A JP10693480 A JP 10693480A JP S5731023 A JPS5731023 A JP S5731023A
- Authority
- JP
- Japan
- Prior art keywords
- data
- writes
- interprets
- transferring
- turns
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
PURPOSE:To greatly shorten a processing time for transferring a data, by providing a common memory circuit between control parts, and transferring the data as a block. CONSTITUTION:In case when data is transferred to a subcontrol part SP3 from a main control part MP1, at first the MP1 writes the data and an execution indicating condition of the SP3 in a communication memory circuit CM4, and after that, turns on a select signal 12. When the signal 12 is turned on, the SP3 turns off a ready signal 13, and sends back a response to the MP1. Subsequently, the CM4 is changed over to an address space of the SP3, interprets the contents of the CM4, which have been written by the MP1, and outputs the data to an output apparatus and processes it. In case when data is transferred to the MP1 from the SP3, the MP1 writes an input command, a data length, etc. in the CM4, and after that, the SP3 interprets the command. Subsequently, the SP3 writes the data in the CM4 from an input apparatus. The MP1 processes the data in the CM4 after confirming that this writing has ended.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10693480A JPS5731023A (en) | 1980-08-04 | 1980-08-04 | Interface system in device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10693480A JPS5731023A (en) | 1980-08-04 | 1980-08-04 | Interface system in device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5731023A true JPS5731023A (en) | 1982-02-19 |
Family
ID=14446220
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10693480A Pending JPS5731023A (en) | 1980-08-04 | 1980-08-04 | Interface system in device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5731023A (en) |
-
1980
- 1980-08-04 JP JP10693480A patent/JPS5731023A/en active Pending
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