JPS6446151A - Information processor - Google Patents

Information processor

Info

Publication number
JPS6446151A
JPS6446151A JP20084487A JP20084487A JPS6446151A JP S6446151 A JPS6446151 A JP S6446151A JP 20084487 A JP20084487 A JP 20084487A JP 20084487 A JP20084487 A JP 20084487A JP S6446151 A JPS6446151 A JP S6446151A
Authority
JP
Japan
Prior art keywords
circuit
memories
request
processor
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20084487A
Other languages
Japanese (ja)
Inventor
Hiroshi Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP20084487A priority Critical patent/JPS6446151A/en
Publication of JPS6446151A publication Critical patent/JPS6446151A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To shorten the writing time for a cell test, a clearing action, etc., at the start carried out after turning on a power source by carrying out parallel and simultaneous writing jobs for all memories connected to the same bus via a processor. CONSTITUTION:An output signal is sent to a write request generating circuit 15 from a processing circuit 11 when a processor 10 performs the parallel and simultaneous writing jobs for all memories 30-1-30-n via firmware. The circuit 15 produces a simultaneous writing request and sends it to a memory selection circuit 16, a request control circuit 17 and a command control circuit respectively. Then selection signals, request signals and commands are outputted to the memories 30-1-30-n from those circuits 16-18. While the memory 30 knows that all memories are selected by a memory selection deciding circuit 31 and sends a start signal to a control circuit 34. Then an address system circuit 35 and a decoder circuit 36 are controlled and address data and write data are outputted to a RAM 38. Thus the writing time is shortened for an information processor.
JP20084487A 1987-08-13 1987-08-13 Information processor Pending JPS6446151A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20084487A JPS6446151A (en) 1987-08-13 1987-08-13 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20084487A JPS6446151A (en) 1987-08-13 1987-08-13 Information processor

Publications (1)

Publication Number Publication Date
JPS6446151A true JPS6446151A (en) 1989-02-20

Family

ID=16431152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20084487A Pending JPS6446151A (en) 1987-08-13 1987-08-13 Information processor

Country Status (1)

Country Link
JP (1) JPS6446151A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100831621B1 (en) * 2007-07-26 2008-05-27 (주)리드팜 The plant extracts composition for the blood glucose reducing action

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100831621B1 (en) * 2007-07-26 2008-05-27 (주)리드팜 The plant extracts composition for the blood glucose reducing action

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