JPS57141738A - Data transfer device - Google Patents
Data transfer deviceInfo
- Publication number
- JPS57141738A JPS57141738A JP2751381A JP2751381A JPS57141738A JP S57141738 A JPS57141738 A JP S57141738A JP 2751381 A JP2751381 A JP 2751381A JP 2751381 A JP2751381 A JP 2751381A JP S57141738 A JPS57141738 A JP S57141738A
- Authority
- JP
- Japan
- Prior art keywords
- interruption
- data chain
- channel
- processing
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Abstract
PURPOSE:To prevent the reduction in processing ability of a channel controlling section, by constituting the device so that an interruption is generated from a channel only when no data chain processing can be done at the interruption from a buffer controlling section. CONSTITUTION:During the seccession of data transfer, when a channel command word CWC with small byte count is kept with a data chain, a channel controlling section 1 sets a data chain mask FF13 via a bus 103 and stops the processing of data chain. Further, when the present byte count register 10 goes to 0 and the next byter count register 11 is used, a signal is transmitted from a byte count controoling section 14 to a bus 109, and an AND condition with a value of the FF13 given via a bus 108 is taken and a data chain mask interruption is generated to the control section 1 from an interruption generating circuit 16. The control section 1 receiving the interruption restarts the data chain processing which is stopped and transmits the information relating to the next CCW to a buffer control section 2 and a channel 4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2751381A JPS6048784B2 (en) | 1981-02-26 | 1981-02-26 | data transfer device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2751381A JPS6048784B2 (en) | 1981-02-26 | 1981-02-26 | data transfer device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57141738A true JPS57141738A (en) | 1982-09-02 |
JPS6048784B2 JPS6048784B2 (en) | 1985-10-29 |
Family
ID=12223205
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2751381A Expired JPS6048784B2 (en) | 1981-02-26 | 1981-02-26 | data transfer device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6048784B2 (en) |
-
1981
- 1981-02-26 JP JP2751381A patent/JPS6048784B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6048784B2 (en) | 1985-10-29 |
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