JPS56111952A - Memory control system for microprocessor - Google Patents

Memory control system for microprocessor

Info

Publication number
JPS56111952A
JPS56111952A JP86080A JP86080A JPS56111952A JP S56111952 A JPS56111952 A JP S56111952A JP 86080 A JP86080 A JP 86080A JP 86080 A JP86080 A JP 86080A JP S56111952 A JPS56111952 A JP S56111952A
Authority
JP
Japan
Prior art keywords
memory
control information
memory control
register
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP86080A
Other languages
Japanese (ja)
Inventor
Kana Kamiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP86080A priority Critical patent/JPS56111952A/en
Publication of JPS56111952A publication Critical patent/JPS56111952A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus

Abstract

PURPOSE:To realize a close connection between a microprogram and a memory or the like and thus ensure a highly efficient progress of the microprogram, by setting the memory control information to a register outside the chip and then controlling the memory according to the memory control information. CONSTITUTION:The memory control information is set to the register 5 provided outside the microprocessor chip 1, and the memory 6 is controlled by the control information. For instance, the memory control information is set properly to the internal register 2 within the chip 1 through the internal bus 3, and then transferred to the external register 5 via the external bus 4 together with other information of the memory address and others and at the moment when the memory 6 starts operation. The memory 6 is operated based on the memory control information set to the external register 5.
JP86080A 1980-01-10 1980-01-10 Memory control system for microprocessor Pending JPS56111952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP86080A JPS56111952A (en) 1980-01-10 1980-01-10 Memory control system for microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP86080A JPS56111952A (en) 1980-01-10 1980-01-10 Memory control system for microprocessor

Publications (1)

Publication Number Publication Date
JPS56111952A true JPS56111952A (en) 1981-09-04

Family

ID=11485412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP86080A Pending JPS56111952A (en) 1980-01-10 1980-01-10 Memory control system for microprocessor

Country Status (1)

Country Link
JP (1) JPS56111952A (en)

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