JPS54155743A - Control system of microprocessor - Google Patents

Control system of microprocessor

Info

Publication number
JPS54155743A
JPS54155743A JP6391278A JP6391278A JPS54155743A JP S54155743 A JPS54155743 A JP S54155743A JP 6391278 A JP6391278 A JP 6391278A JP 6391278 A JP6391278 A JP 6391278A JP S54155743 A JPS54155743 A JP S54155743A
Authority
JP
Japan
Prior art keywords
microprogram
output
microprocessor
μpseq2
wcs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6391278A
Other languages
Japanese (ja)
Inventor
Yoshinobu Sano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6391278A priority Critical patent/JPS54155743A/en
Publication of JPS54155743A publication Critical patent/JPS54155743A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to modify the content of a microprogram at a high speed and also to execute it at a high speed, by controlling a microprocessor by the latched output of each memory unit.
CONSTITUTION: Once an instruction is outputted from microprogram storage 16 by the microprogram address output of sequence controller μPSEQ2, μPSEQ2 outputs a new address at the same time when the instruction is latched by register LATCH 14, and during this time, microprocessor ALU19 executes the instruction. To use memory element WCS/M4 as a microprogram storage, assignment SEL.FF3 is set a mode of WCS(writable control storage), and consequently WCS/M4 is disconnected from address bus 1a and data bus 1b to output a microinstruction according to the address output of μPSEQ2.
COPYRIGHT: (C)1979,JPO&Japio
JP6391278A 1978-05-30 1978-05-30 Control system of microprocessor Pending JPS54155743A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6391278A JPS54155743A (en) 1978-05-30 1978-05-30 Control system of microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6391278A JPS54155743A (en) 1978-05-30 1978-05-30 Control system of microprocessor

Publications (1)

Publication Number Publication Date
JPS54155743A true JPS54155743A (en) 1979-12-08

Family

ID=13243010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6391278A Pending JPS54155743A (en) 1978-05-30 1978-05-30 Control system of microprocessor

Country Status (1)

Country Link
JP (1) JPS54155743A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119464A (en) * 1982-12-21 1984-07-10 テキサス・インスツルメンツ・インコ−ポレイテツド Digital processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119464A (en) * 1982-12-21 1984-07-10 テキサス・インスツルメンツ・インコ−ポレイテツド Digital processor

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