JPS5583941A - Microprogram system - Google Patents

Microprogram system

Info

Publication number
JPS5583941A
JPS5583941A JP15794778A JP15794778A JPS5583941A JP S5583941 A JPS5583941 A JP S5583941A JP 15794778 A JP15794778 A JP 15794778A JP 15794778 A JP15794778 A JP 15794778A JP S5583941 A JPS5583941 A JP S5583941A
Authority
JP
Japan
Prior art keywords
address
register
order
read out
microprogram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15794778A
Other languages
Japanese (ja)
Other versions
JPS6051739B2 (en
Inventor
Yutaka Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15794778A priority Critical patent/JPS6051739B2/en
Publication of JPS5583941A publication Critical patent/JPS5583941A/en
Publication of JPS6051739B2 publication Critical patent/JPS6051739B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To omit the hardware which decides the privilege order by setting the address following the start address of the microprogram of the privilege order in the user mode as the illegal order process routine.
CONSTITUTION: The program staus containing the bit which designates the mode of the program under execution is held by program status working register 1, and at the same time the order to be executed is held by order holding register 2. And the first microprogram address is given to main ROM4 from register 2, and then the first microorder is read out of ROM4. And the address of MAPROM is read out from the next microprogram address via the bit to designate the mode of register 1 and the output of register 2. With this address read out, the initial setting is given to counter 7, and at the same timethe microorder to be executed next is transferred to the main ROM from counter 7 to read out the microorder within the main ROM.
COPYRIGHT: (C)1980,JPO&Japio
JP15794778A 1978-12-21 1978-12-21 Micro program method Expired JPS6051739B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15794778A JPS6051739B2 (en) 1978-12-21 1978-12-21 Micro program method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15794778A JPS6051739B2 (en) 1978-12-21 1978-12-21 Micro program method

Publications (2)

Publication Number Publication Date
JPS5583941A true JPS5583941A (en) 1980-06-24
JPS6051739B2 JPS6051739B2 (en) 1985-11-15

Family

ID=15660939

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15794778A Expired JPS6051739B2 (en) 1978-12-21 1978-12-21 Micro program method

Country Status (1)

Country Link
JP (1) JPS6051739B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60193046A (en) * 1984-03-14 1985-10-01 Fujitsu Ltd Detecting system for instruction exception

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0461886U (en) * 1990-10-03 1992-05-27

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60193046A (en) * 1984-03-14 1985-10-01 Fujitsu Ltd Detecting system for instruction exception
JPH0258648B2 (en) * 1984-03-14 1990-12-10 Fujitsu Ltd

Also Published As

Publication number Publication date
JPS6051739B2 (en) 1985-11-15

Similar Documents

Publication Publication Date Title
JPS51147924A (en) Memory unit
JPS55105763A (en) Address instruction system
JPS5220735A (en) Microprogram controlled computer system
JPS5464439A (en) Address designation system
JPS5344134A (en) Microprogram control system
JPS5583941A (en) Microprogram system
JPS5423343A (en) Microprogram controller
JPS5424547A (en) Control system for memory extension
JPS5725068A (en) Vector processor
JPS53129539A (en) Insersion system of word processor
JPS5235929A (en) Program reservation system
JPS5544662A (en) Input/output program control unit
JPS53142841A (en) Data processor
JPS52129252A (en) Program processing unit
JPS5346245A (en) Microprogram controller
JPS55159257A (en) Debugging system
JPS5474650A (en) Stack control system
JPS52122063A (en) Branch return instruction processing unit
JPS5617402A (en) Programmable sequence controller
JPS5448459A (en) Control unit of instruction advance fetch
JPS5271137A (en) Buffer memory
JPS5563444A (en) Microprogram interruption control circuit
JPS5311549A (en) Debugging unit for software
JPS53140948A (en) Interrupt processing system
JPS5437654A (en) Data erase system for register