JPS5563444A - Microprogram interruption control circuit - Google Patents

Microprogram interruption control circuit

Info

Publication number
JPS5563444A
JPS5563444A JP13672178A JP13672178A JPS5563444A JP S5563444 A JPS5563444 A JP S5563444A JP 13672178 A JP13672178 A JP 13672178A JP 13672178 A JP13672178 A JP 13672178A JP S5563444 A JPS5563444 A JP S5563444A
Authority
JP
Japan
Prior art keywords
level
interruption
microprogram
control circuit
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13672178A
Other languages
Japanese (ja)
Other versions
JPS6115453B2 (en
Inventor
Masakazu Okada
Seiichi Yasumoto
Hitoshi Fushimi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13672178A priority Critical patent/JPS5563444A/en
Publication of JPS5563444A publication Critical patent/JPS5563444A/en
Publication of JPS6115453B2 publication Critical patent/JPS6115453B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To perform level transit without interruption the processing, by adding the level control circuit to the address control section and using the execution timing of microprogram to the timing of interruption processing as it is.
CONSTITUTION: Taking the present execution program level as (0,0) and the interruption level as (0,1), the output of the comparator COMP 8 is "1", FF11 is set and the register 10 is triggered. Although the execution program level (0,0) is indicated to the lower 2 bits of the 4-bit register LEVEL10, the setting of FF11 gives the lower 2 bit of LEVEL10 to the upper 2 bits and the interruption level to the lower 2 bits. Thus, the execution level moves from (0,0) to (0,1).
COPYRIGHT: (C)1980,JPO&Japio
JP13672178A 1978-11-08 1978-11-08 Microprogram interruption control circuit Granted JPS5563444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13672178A JPS5563444A (en) 1978-11-08 1978-11-08 Microprogram interruption control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13672178A JPS5563444A (en) 1978-11-08 1978-11-08 Microprogram interruption control circuit

Publications (2)

Publication Number Publication Date
JPS5563444A true JPS5563444A (en) 1980-05-13
JPS6115453B2 JPS6115453B2 (en) 1986-04-24

Family

ID=15181933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13672178A Granted JPS5563444A (en) 1978-11-08 1978-11-08 Microprogram interruption control circuit

Country Status (1)

Country Link
JP (1) JPS5563444A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61214032A (en) * 1985-03-20 1986-09-22 Hitachi Ltd Interruption control system
JPS63296139A (en) * 1987-05-27 1988-12-02 Fujitsu Ltd Interrupt control circuit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09310921A (en) * 1996-05-23 1997-12-02 Nippon Shizen Kagaku Sogo Kenkyusho:Kk Heat storage type hot-water device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61214032A (en) * 1985-03-20 1986-09-22 Hitachi Ltd Interruption control system
JPS63296139A (en) * 1987-05-27 1988-12-02 Fujitsu Ltd Interrupt control circuit

Also Published As

Publication number Publication date
JPS6115453B2 (en) 1986-04-24

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