JPS63175251U

JPS63175251U -

Info

Publication number: JPS63175251U
Application number: JP17938586U
Authority: JP
Priority date: 1986-11-21
Filing date: 1986-11-21
Publication date: 1988-11-14

Description

[Brief explanation of the drawing]

第１図は本考案システムの概念図、第２図は第
１図におけるパリテイ・ジエネレータ付カード内
に設けられているパリテイチエツク回路の一例を
示す構成ブロツク図である。ＳＢ……制御バス、ＡＤＢ……アドレス・デー
タ・バス、Ａ１，Ａ２……パリテイ・ジエネレー
タ付カード、Ｂ１，Ｂ２……パリテイ・ジエネレ
ータの無いカード、ＰＡ……パリテイビツトライ
ン、ＰＥＮ……パリテイイネエブルライン、ＰＧ
……パリテイ・ジエネレータ。 FIG. 1 is a conceptual diagram of the system of the present invention, and FIG. 2 is a block diagram showing an example of a parity check circuit provided in the card with a parity generator shown in FIG. SB...control bus, ADB...address data bus, A1, A2...card with parity generator, B1, B2...card without parity generator, PA...parity bit line, PEN...parity Good line, PG
... Parity Generator.

Claims

[Claim for Utility Model Registration] An address/data bus, a control bus, and a parity bit line for transmitting parity bits;
a parity enable line for transmitting a signal indicating whether the parity bit is valid or invalid; a card with a parity generator coupled to the address data bus, the control bus, the parity bit line and the parity enable line; and the address data bus. - A system comprising a card without a parity generator coupled to a data bus and a control bus, respectively, wherein in the card with a parity generator, a parity check circuit including a parity generator is connected to the parity enable line. When the signal is at "H" level, parity is calculated from the data transmitted via the address/data bus, and a parity check is performed by comparing the parity with the parity transmitted via the parity bit line. An address/data bus system characterized in that the parity check described above is not performed when the signal on the parity enable line is at the "L" level.