JPS5510679A - Character display controller - Google Patents

Character display controller

Info

Publication number
JPS5510679A
JPS5510679A JP8376278A JP8376278A JPS5510679A JP S5510679 A JPS5510679 A JP S5510679A JP 8376278 A JP8376278 A JP 8376278A JP 8376278 A JP8376278 A JP 8376278A JP S5510679 A JPS5510679 A JP S5510679A
Authority
JP
Japan
Prior art keywords
sent out
gate signals
display controller
register
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8376278A
Other languages
Japanese (ja)
Other versions
JPS5843748B2 (en
Inventor
Yoshimi Miyamoto
Masatoshi Horiguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP53083762A priority Critical patent/JPS5843748B2/en
Publication of JPS5510679A publication Critical patent/JPS5510679A/en
Publication of JPS5843748B2 publication Critical patent/JPS5843748B2/en
Expired legal-status Critical Current

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  • Document Processing Apparatus (AREA)

Abstract

PURPOSE:To obtain a character display controller with the short processing time, by performing format processing by its hardware. CONSTITUTION:Character pattern data expressed by a matrix is supplied from processor 15 to data bus 16 and at every time of the supply, a storobe signal is sent out and counted by counter 18. The count content is decoded by decoder 19 and gate signals GS1 to GS5 are sent out. Corresponding to gate signals GS1 to GS5, selection control part 21 is controlled to supply character pattern data in the line format from processor 15 to 1st and 2nd registers 22 and 23. According to timing signal 24 generated by timing generation part, either content of 1st register 22 or 2nd register 23 is sent out to the display unit via data line 28 by gate signals GS1 to GS5 under the control of output control part 25.
JP53083762A 1978-07-10 1978-07-10 Character display control device Expired JPS5843748B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53083762A JPS5843748B2 (en) 1978-07-10 1978-07-10 Character display control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53083762A JPS5843748B2 (en) 1978-07-10 1978-07-10 Character display control device

Publications (2)

Publication Number Publication Date
JPS5510679A true JPS5510679A (en) 1980-01-25
JPS5843748B2 JPS5843748B2 (en) 1983-09-28

Family

ID=13811579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53083762A Expired JPS5843748B2 (en) 1978-07-10 1978-07-10 Character display control device

Country Status (1)

Country Link
JP (1) JPS5843748B2 (en)

Also Published As

Publication number Publication date
JPS5843748B2 (en) 1983-09-28

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