JPS5480047A - Microprogram control system - Google Patents

Microprogram control system

Info

Publication number
JPS5480047A
JPS5480047A JP14706777A JP14706777A JPS5480047A JP S5480047 A JPS5480047 A JP S5480047A JP 14706777 A JP14706777 A JP 14706777A JP 14706777 A JP14706777 A JP 14706777A JP S5480047 A JPS5480047 A JP S5480047A
Authority
JP
Japan
Prior art keywords
rom
register
rom12
output
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14706777A
Other languages
Japanese (ja)
Inventor
Tokumitsu Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14706777A priority Critical patent/JPS5480047A/en
Publication of JPS5480047A publication Critical patent/JPS5480047A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To reduce the bit width of ROM and to increase the process velocity by providing the control ROM in addition to the ROM to store the microprogram with no addition of the ROM's access time to the operation time and preparing the information necessary for the operation before the process cycle.
CONSTITUTION: The following units are installed: 1st ROM12 to store the microprogram; address controller 11 to give control to the address to give an access to ROM12; and 1st data register 13 to ratch the information of ROM12 via the address designated by controller 11. Furthermore, 2nd ROM15 is added to receive an access by part of the output ratched to register 13 and then to deliver the control signal, along with 2nd register 16 to ratch the output of ROM15, and arithmetic logic circuit 18 to carry out the arithmetic process by the output of register 16. Thus, the control information of the next order plus the further subsequent order are fetched under the arithmetic process of a certain order.
COPYRIGHT: (C)1979,JPO&Japio
JP14706777A 1977-12-09 1977-12-09 Microprogram control system Pending JPS5480047A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14706777A JPS5480047A (en) 1977-12-09 1977-12-09 Microprogram control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14706777A JPS5480047A (en) 1977-12-09 1977-12-09 Microprogram control system

Publications (1)

Publication Number Publication Date
JPS5480047A true JPS5480047A (en) 1979-06-26

Family

ID=15421725

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14706777A Pending JPS5480047A (en) 1977-12-09 1977-12-09 Microprogram control system

Country Status (1)

Country Link
JP (1) JPS5480047A (en)

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