JPS57172461A - Multi-processor system - Google Patents

Multi-processor system

Info

Publication number
JPS57172461A
JPS57172461A JP5888081A JP5888081A JPS57172461A JP S57172461 A JPS57172461 A JP S57172461A JP 5888081 A JP5888081 A JP 5888081A JP 5888081 A JP5888081 A JP 5888081A JP S57172461 A JPS57172461 A JP S57172461A
Authority
JP
Japan
Prior art keywords
common
operation code
interruption
bus
executed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5888081A
Other languages
Japanese (ja)
Inventor
Genichi Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shimadzu Corp
Shimazu Seisakusho KK
Original Assignee
Shimadzu Corp
Shimazu Seisakusho KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shimadzu Corp, Shimazu Seisakusho KK filed Critical Shimadzu Corp
Priority to JP5888081A priority Critical patent/JPS57172461A/en
Publication of JPS57172461A publication Critical patent/JPS57172461A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To reduce processing time in an exclusive bus system and to make both sides of software/hardware of data replacement in the common memory of bus coupling system, easy by microprogramming with a multi-operation code. CONSTITUTION:A control sustem for CPUs 1 and 2 is microprogrammed with a common operation code coupled with common buses 18 and 21, and when the common operation code is executed, a common bus control signal CRBRQ is transmitted and a series of bus control is made in response to a response input signal CRBAK. When a multi-operation code is executed, an EQ' is transmitted and when an EI is inputted, a multi-use interruption is generated, and calls such as program pointer and status and save of each register interruption are made from a specified area of an exclusive memory 8. The multi-use interruption can be masked with the software and the interruption can be ignored. When processor units 1 and 2 are in operation, the processing is made independently and in parallel to achieve the maximum processing speed.
JP5888081A 1981-04-17 1981-04-17 Multi-processor system Pending JPS57172461A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5888081A JPS57172461A (en) 1981-04-17 1981-04-17 Multi-processor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5888081A JPS57172461A (en) 1981-04-17 1981-04-17 Multi-processor system

Publications (1)

Publication Number Publication Date
JPS57172461A true JPS57172461A (en) 1982-10-23

Family

ID=13097070

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5888081A Pending JPS57172461A (en) 1981-04-17 1981-04-17 Multi-processor system

Country Status (1)

Country Link
JP (1) JPS57172461A (en)

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