JPS5585940A - Processing system for interruption input - Google Patents

Processing system for interruption input

Info

Publication number
JPS5585940A
JPS5585940A JP15883078A JP15883078A JPS5585940A JP S5585940 A JPS5585940 A JP S5585940A JP 15883078 A JP15883078 A JP 15883078A JP 15883078 A JP15883078 A JP 15883078A JP S5585940 A JPS5585940 A JP S5585940A
Authority
JP
Japan
Prior art keywords
interruption
interruption input
input
address
processing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15883078A
Other languages
Japanese (ja)
Inventor
Hiroshi Tanaka
Yukio Urushibata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15883078A priority Critical patent/JPS5585940A/en
Publication of JPS5585940A publication Critical patent/JPS5585940A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable high speed transmission in low cost, by providing the register registrating the address of the interruption input with the processor and transmitting the input board of interruption to a given address.
CONSTITUTION: By providing the registers REG121WREG124 registrating the address of interruption input outputted from the interruption input board with the processors CPU11WCPU14, when interruption input is taken place, the control unit 11 references the registers REG121WREG124 and transmits the corresponded interruption input to the corresponded processors CPU11WCPU14.
COPYRIGHT: (C)1980,JPO&Japio
JP15883078A 1978-12-22 1978-12-22 Processing system for interruption input Pending JPS5585940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15883078A JPS5585940A (en) 1978-12-22 1978-12-22 Processing system for interruption input

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15883078A JPS5585940A (en) 1978-12-22 1978-12-22 Processing system for interruption input

Publications (1)

Publication Number Publication Date
JPS5585940A true JPS5585940A (en) 1980-06-28

Family

ID=15680312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15883078A Pending JPS5585940A (en) 1978-12-22 1978-12-22 Processing system for interruption input

Country Status (1)

Country Link
JP (1) JPS5585940A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008074238A (en) * 2006-09-21 2008-04-03 Mazda Motor Corp Seat device
US9785586B2 (en) 2011-11-11 2017-10-10 Fujitsu Limited Electronic computer and interrupt control method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50128951A (en) * 1974-03-29 1975-10-11
JPS5158841A (en) * 1974-11-20 1976-05-22 Hitachi Ltd
JPS5223235A (en) * 1975-08-18 1977-02-22 Nec Corp Input/output multiprocessor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50128951A (en) * 1974-03-29 1975-10-11
JPS5158841A (en) * 1974-11-20 1976-05-22 Hitachi Ltd
JPS5223235A (en) * 1975-08-18 1977-02-22 Nec Corp Input/output multiprocessor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008074238A (en) * 2006-09-21 2008-04-03 Mazda Motor Corp Seat device
US9785586B2 (en) 2011-11-11 2017-10-10 Fujitsu Limited Electronic computer and interrupt control method

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