JPS5492143A - Control system for pipeline arithmetic unit - Google Patents

Control system for pipeline arithmetic unit

Info

Publication number
JPS5492143A
JPS5492143A JP16045677A JP16045677A JPS5492143A JP S5492143 A JPS5492143 A JP S5492143A JP 16045677 A JP16045677 A JP 16045677A JP 16045677 A JP16045677 A JP 16045677A JP S5492143 A JPS5492143 A JP S5492143A
Authority
JP
Japan
Prior art keywords
arithmetic unit
operand
aok
pipeline arithmetic
sent back
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16045677A
Other languages
Japanese (ja)
Inventor
Masaaki Inao
Nobuaki Kume
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16045677A priority Critical patent/JPS5492143A/en
Publication of JPS5492143A publication Critical patent/JPS5492143A/en
Pending legal-status Critical Current

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  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE: To simplify constitution, by stopping the all pipeline arithmetic units by stopping a clock when the supplying of input data to the lst arithmetic unit stops.
CONSTITUTION: Clock signal generator CLK stops sending out clocks if signals BOK and COK indicating the reception from the VC side are not sent back to B and C operand buffers OB and OC respectively when B operand data and C operand data are requested to vector controller VC while the pipeline arithmetic unit of the array processor is executing vector additon. In the same way, the supplying of clocks from CLK stops if signal AOK is not sent back when the pipeline arithmetic unit requests VC to transfer A operand data in operand buffer OA. Further, ×AOK indicates the that no AOK is sent back, and ×BOK and ×COK are the same.
COPYRIGHT: (C)1979,JPO&Japio
JP16045677A 1977-12-29 1977-12-29 Control system for pipeline arithmetic unit Pending JPS5492143A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16045677A JPS5492143A (en) 1977-12-29 1977-12-29 Control system for pipeline arithmetic unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16045677A JPS5492143A (en) 1977-12-29 1977-12-29 Control system for pipeline arithmetic unit

Publications (1)

Publication Number Publication Date
JPS5492143A true JPS5492143A (en) 1979-07-21

Family

ID=15715318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16045677A Pending JPS5492143A (en) 1977-12-29 1977-12-29 Control system for pipeline arithmetic unit

Country Status (1)

Country Link
JP (1) JPS5492143A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60118976A (en) * 1983-11-30 1985-06-26 Fujitsu Ltd Pipeline control system
JPS60167029A (en) * 1984-10-05 1985-08-30 Hitachi Ltd Data processor
JPS60222969A (en) * 1984-04-20 1985-11-07 Fujitsu Ltd Pipeline controlling circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60118976A (en) * 1983-11-30 1985-06-26 Fujitsu Ltd Pipeline control system
JPH0316665B2 (en) * 1983-11-30 1991-03-06 Fujitsu Ltd
JPS60222969A (en) * 1984-04-20 1985-11-07 Fujitsu Ltd Pipeline controlling circuit
JPH0321941B2 (en) * 1984-04-20 1991-03-25 Fujitsu Ltd
JPS60167029A (en) * 1984-10-05 1985-08-30 Hitachi Ltd Data processor
JPS6214855B2 (en) * 1984-10-05 1987-04-04 Hitachi Ltd

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