JPS60167029A - Data processor - Google Patents

Abstract

PURPOSE:To prevent intermittent data from being read erroneously by providing a means which detects whether or not there is data to be read present in a storage means which has storage locations to be assigned in order. CONSTITUTION:Distributing logical circuits 911 and 912 are interposed between pipeline type arithmetic units 901, 902, and 903 and first-in first-out storage devices (FiFo memory) 921-925. The distributing logical circuits 911 and 912 consist of plural multi-input selector groups and function to assign the FiFo memories to input origins and output destinations of respective units with an external indication. Each FiFo memory has a means which detects whether or not there is data to be read present in the memory and inhibits reading operation when not. Therefore, write data are generated intermittently and transferred correctly from one arithmetic unit to another.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention provides a first-in/first-out storage device i (hereinafter referred to as FiFO memory) that is capable of correctly reading data from a plurality of arithmetic units even if writing is performed intermittently. The present invention relates to a data processing device that can be selectively connected to a data processor.

Here, the FiFO memory is defined as a storage device that can read information in order from the first written information, that is, the oldest information.

[Background of the invention]

A prior art related to a high-speed data processing device that operates multiple arithmetic units simultaneously is disclosed in US Pat. No. 4,128,880, for example.

There is a method of selectively coupling arithmetic units using vector registers.

This method, called chaining, is based on the premise that one arithmetic unit continuously outputs valid data without any break, and another arithmetic unit inputs valid data continuously without any break. However, it does not operate correctly when data is transferred intermittently, such as when reading data from a storage device. That is, there is a risk that data that has not yet been written may be read by mistake.

[Purpose of the invention]

An object of the present invention is to selectively combine a plurality of arithmetic units and operate them simultaneously, so that even if data is intermittently output from the arithmetic units, correct data can be input to subsequent arithmetic units as valid data. The purpose of the present invention is to provide a processing device.

[Summary of the Invention] In order to achieve such an object, the present invention provides a storage means having storage locations that are sequentially specified in order to store data, and a storage means that executes an operation on input and corresponds to the operation result. The storage means is selectively connected to the plurality of calculation means so that the data from the storage means is given as an input to the calculation means, and the data output of the calculation means is sequentially given to the storage means. It controls the storage means to sequentially read data to the connected selection means and the selected calculation means, detects the existence of data to be read from the storage means, and when the data does not exist, reads the data from the storage means. and read control means for prohibiting continuous reading operation.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples.

First, in order to clarify the configuration and function of the FiFO memory used in the present invention, the FiFO memory between computing units is
The configuration and operation of a data processing device when fixedly coupled using O memory as an intermediary will be explained with a focus on FiFO memory,
Finally, with reference to FIG. 7, a configuration of a data processing apparatus according to an embodiment of the present invention, which can be selectively coupled using the aforementioned FiFO memory as an intermediary, will be described according to instructions from a program.

In recent years, as shown in FIG. 1, FiFO memories have come to be applied to pipeline type arithmetic processing devices. In the figure, a pipeline type arithmetic unit 1 surrounded by a dashed line consists of a pipeline arithmetic unit 2 and a pipeline control logic circuit 3 for controlling this arithmetic unit, and receives data l1s30 from arithmetic units 4 and 5. 3
It receives input data (one-bit or multiple-bit data) via data line 32 and sends the operation result to another arithmetic unit 6 via data line 32. FiFO memory 20゜2
1.22 is provided between units as a buffer for input data and calculation results. In other words, the input data from the arithmetic unit 4 (from the perspective of the unit 4, the arithmetic results of the unit 4) is input from the data line 30 to the FiFO memory 20, and then passes through the data line 10 to the pipeline operation in the unit 1. is input to device 2. FiFO memory 21
and 22 are similar, and data lines 11 and 12 are used.

There are two advantages when using such a FiFO memory as a buffer.

(1) Measures against interruptions in input data from calculation units 4 and 5. Multi-input pipeline arithmetic unit 2 as shown in Figure 1
In general, many pairs of input data having the same number need to be input at the same time. Here, consider a case where input data with a certain number has arrived from the arithmetic unit 4, but the corresponding input data with the same number from another arithmetic unit 5 is delayed in arrival for some reason. The FiFO memory 20 accepts data sent out in each cycle via the data line 3', and receives data sent to the unit 1 via the data line 10 and input data from other units 5'. used to delay the arrival of During this time, invalid data is input to the pipeline arithmetic unit 2, and the corresponding operation result is also invalid. However, the pipeline control logic circuit 3 prevents this invalid output from being sent to other units 6. is controlled.

(2) The reception of the unit 6 is a rejection measure, and the unit 6 may refuse to accept data from the data line 32.

The FiFO memory 22 is used to temporarily buffer the calculation results from the pipeline calculation unit 2 via the data line 12 and to make the data wait until the unit 6 can accept it.

In this way, when the above-mentioned data discontinuity phenomenon occurs, a FiFO
It is effective to provide memory. The functions required for this FiFO memory are as follows.

(A) Reading and writing must be possible simultaneously within the pipeline pitch time.

(B) Written data can be read in a short time.

Conventionally, the storage element of such high-speed FiFO memory has been a flip-flop (hereinafter referred to as FF), which is a combination of gates.
In many cases, either a latch or a general memory element (which can be read or written once in one memory cycle) was used. Although the former is sufficiently fast, it has the disadvantage that the number of gates is enormous in order to construct a large-capacity FiFO memory. on the other hand,
In order to satisfy the above function (A) in a general memory element, it is necessary to execute two memory cycles within the pitch time of the pipeline. However, with current pipeline technology and high-speed memory device technology, it is difficult to obtain a large-capacity memory device that can execute - number of memory cycles in half the pipeline pitch time.

The FiFO memory used in the present invention includes a plurality of writable and readable data banks, a mode specifying means for repeatedly specifying the plurality of data banks to the write mode, and a mode specifying means for specifying the write mode by repeating the plurality of data banks, and a mode specifying means for specifying the write mode by repeatedly selecting the plural data banks. The present invention is characterized in that it includes a write/read control means that writes data to a data bank, reads data from a data bank that is not specified in the write mode, and outputs the data in the order in which it is received.

FIG. 2 is an overall block diagram of the FiFO memory used in the present invention. This FiFO memory is F in Figure 1.
It is applicable to any of the iFO memories 20, 21, and 22.

In FIG. 2, 47 and 48 are data banks (hereinafter simply referred to as banks), which can be written and read independently of each other.

Each data bank 47,48 consists of one random access memory (hereinafter referred to as RAM).

Note that it is sufficient if there are two or more banks.

It goes without saying that each bank may be configured with a plurality of RAMs depending on the required capacity and word configuration.

Data sent from the outside is written to banks 47 and 48 in the order in which it was sent.

For example, the first data sent is bank 4.
7, and the next data No. 1 sent is bank 48.
Then, the second data sent next goes to bank 47, the third data sent next goes to bank 48,
. . . are repeatedly written to banks 47 and 48 in order.

Therefore, bank 47 has 0, 2, 4 .・・・・・・
.

Since the 2nth (n is an integer) data, that is, the even numbered data, is written in order, it is called an even bank. Bank 48 has 1, 3, 5. .......

Since data No. 2n+1, that is, odd numbered data, is written in order, it will be called an odd numbered bank.

Reference numeral 41 denotes a mode designation circuit for repeatedly designating which bank among the banks 47 and 48 is in a writable mode at a constant cycle. Now, the writable mode is called W mode, and the readable mode is called R mode. The mode designation circuit 41 is 'O#l, #11. ．． ．． "tQn, u
"011.01." is repeatedly output at a constant cycle as ln, . . . The output of the mode designation circuit 41 is "
0'', the even bank 47 is in W mode and the odd bank 48 is in R mode.The output of the circuit 41 is II
177, the even bank 47 is in the R mode and the odd bank 48 is in the R mode, contrary to the case of zt Oep. Therefore, the banks 47 and 48 receive mode designations of R mode and W mode repeatedly at a constant cycle so that the modes are different from each other at each time point, and are received by the mode designation circuit 41.

100 is a bank 47 consisting of circuits 42 to 46.49.
．． 48 write/read control circuits. circuit 10
0 means even bank 4 when even number data is input.
If 7 is in W mode, this data is immediately written to even bank 47.

If the even bank 47 is not in the W mode, that is, if it is in the R mode, it waits until it becomes the W mode, and when it becomes the W mode, this data is written. The same applies to writing odd numbered data.

Further, when there is a read request and the data to be read is written in the even bank 47, if the even bank 47 is in the R mode,
Read immediately from If the even bank 47 is in the W mode, it waits until it becomes the R mode, and then reads out the data when it becomes the R mode.

The configuration of the FiFO memory shown in FIG. 2 enables reading and writing at the same time. For example, even bank 47
Data can be read from the odd bank 48 at the same time as writing data to the odd bank 48. In FIG. 2, thick signal lines represent multiple signal lines.

Next, the operation of this FiFO memory will be explained.

In FIG. 2, when a write request is received (a write request arrives), the write request instruction signal WREQ on the signal line 33 is #IN, and the value of the data signal VDATA on the data line 30 is write data. be. Signals WRHQ and wDATA are input from a first external device, such as the arithmetic unit 4, to a write control circuit 42 (hereinafter referred to as W control circuit). The W control circuit receives the signal VR
Based on the EQ, it has means for detecting the arrival of a write request, receiving write data from the signal 1i1DATA, and detecting the arrival number of the arriving write request. Suppose that it is detected that the arrival number of the write request is Nth, and whether N is an even number or an odd number determines whether the data bank to be written is an even bank or an odd bank. On the other hand, since the output signal SW of the mode designation circuit 41 described above designates the W mode bank, when the data bank determined by the evenness of N matches the data bank designated by the signal SW as the W mode, the W control circuit 4
2 outputs the address determined by the value of the upper bit excluding the lower 1 bit in the binary representation of N to the signal WAH on the signal line 93, and outputs the write instruction signal WE on the signal line 93.
Write data to even banks is output to signal 5DRH on signal @82, and write data to odd banks is output to signal 5DRO on signal line 83. When a write request arrives If there is a possibility that the banks do not match, a means is required to store the existence of the write request and the write data until the banks match.

A detailed example of the means will be described later with reference to FIG. 9.
Initial value setting signal 5TAR input via signal line 39
By T, the W control circuit 42 is set to an initial state as described later.

A circuit 44 surrounded by a dashed line receives signals 1wl59, 5 in response to the mode designation signal SW and the write enable signal WE.
8 via the write command signal WEE.

This is a write signal generation circuit that outputs WEO to banks 47 and 48, respectively. The AND gate 441 of the circuit 44 indicates that the signal SW is "0" and the bright signal WE is II 11
Only when the condition 1 is satisfied, write command signal WEE
'1' is output to the even bank 47. In this way, even bank 47 is in W mode (signal WE is in II O#
l) and there is data to be written (signal W
When E is 01 #l) '1' is output to the even bank 47 as the write command signal WEE.

The AND gate 442 outputs II 117 to the odd bank 48 as the write command signal WEO only when the conditions that the signal Sw is 1 and the signal WE is sr I g are satisfied. In this way, when the odd bank 48 is in the W mode (signal SW is #l 1 pg) and there is data to be written (when the signal WE is '1''), the write command signal WEO to the odd bank 48 is It I II is output.

A circle marked on one side of the input of AND gate 441 indicates that the input signal is inverted.

The selection circuit 45 operates in response to the mode designation signal sw to selectively output the write address WAH described above to one of the banks 47 and 48.

The circuit 45 consists of selectors 451 and 452. When the mode designation signal SW is II O#, the selector 451 selectively outputs the signal WAH from the write address signal WAH described above and the read address signal RAH described later to the signal line 57. Therefore, when the even bank 47 is in the write mode (signal SW is II On), the write address WAH is output to the wave number bank 47. When the signal SW is II II II, the selector 52 selectively outputs a read address RAH, which will be described later, to the even bank 47 . The selector 452 selectively outputs a read address RAH, which will be described later, to the signal line 56 when the signal SW is #OII, and selectively outputs a write address WAH to the signal line 56 when the signal SW is II 1 F+. Therefore, the write address WAH is output to the odd bank 48 when the odd bank 48 is in the write mode (when the signal SW is tt I H). Selector 45I.

452 and 461, 491, which will be described later, are input from the upper left (selector 45) when the signal SW applied from above is '0''.
1 selects the input from the address line 93) and outputs the signal S.
When W is II I H, input from the lower left (selector 45
1 has the function of selecting the input from the address line 99) and outputting it to the right output line (signal line 57 in 451).

The selection circuit 46 responds to the signal SW to select the above-mentioned even bank write data signal 5DRII! It selectively outputs the write data signal SHO for odd-numbered banks and consists of a selector 461. The selector 461 has a signal SW of 0''
At this time, the signal line 82 is selected and the data signal 5DRE is output to the signal lines 54 and 55. When the signal SW is #1gg, the signal line 83 is selected and the data signal 5DRO is output to the signal line 54.55. Therefore, when even bank 47 is in W mode (signal SW is IIO#), even bank write data signal 5DRE is applied to banks 47 and 48.

Therefore, when an even-numbered write request arrives at the FiFO memory, when the even-numbered bank is in W mode, the signal 111)1 is input to the write terminal WET of the even-numbered bank 47, and the aforementioned write address is input to the address terminal AT. The signal WAH is input, this data signal 5ORE is input to the data terminal DIT, and the even bank write data signal 5DRE is written to the even bank 47. However, as described above, when the even bank 47 is in the W mode (when the signal SW is tt On), the odd bank 48
is in the R mode and the signal SW is '0'', so the write command signal WEO, which is the output of the AND gate 442, becomes 0'', and writing to the odd bank 48 is prohibited, so the even bank write data 5DRH is written to the odd bank 48. It will never be written.

When odd bank 48 is in W mode (signal SW is Bi), odd bank write data signal 5DRO is applied to banks 47 and 48. However, for the same reason as mentioned above, this data signal 5DRO is not written to the even bank 47, but is written to the odd bank 48.

Note that instead of the selector 461, the signal lines 82 and 55 are connected so that the signal 5DRE is always applied to the even bank 47, and the signal lines 83 and 54 are connected, so that the signal 5DRE is always applied to the even bank 47.
DRO may always be applied to odd banks 48. However, if the selector 461 is used, the signal line 55
and 54 can be shared, and banks 47, 48 and W
Wiring of signal lines between the control circuits 42 is simplified.

In this way, data number 0 is placed at address 0 of even bank 47, data number 1 is placed at address 0 of odd bank 48, data number 2 is placed at address 1 of even bank 47, and data number 3 is placed at address 1 of even bank 47. 48, number 1, etc.
Data is automatically and alternately written into banks 47 and 48 according to the order in which they are received without any external designation of an address.

Note that banks 47 and 48 have the following input/output terminals. WET is a write command signal input terminal, and a write command signal WEE to the even bank 47 or a write command signal WEO to the odd bank 48 is input to the terminal WET. A
T is a memory address input terminal, and the memory address AE for the even bank 47 or the memory address AO for the odd bank 48 is input to the terminal AT. DIT is a write data input terminal, and a data signal DIE or DIO is input to the terminal DIT.

DOT is a read data output terminal, and even bank 47
The read data DOE from the terminal DOT is connected to the data line 471.
The read data DOO is output from the terminal DOT of the odd bank 48 to the data line 481. Terminal WET
When the input is II l #l, banks 47 and 48 store the data at the data terminal DIT at the address indicated by the address signal input to the address input terminal AT.

When the input to the terminal WET is 0'', the bank 47.48 reads the data stored at the address indicated by the address signal input to the address input terminal. The input/output terminals include a power supply terminal, a chip select terminal, an output enable terminal, and the like.

Now that the writing operation has been explained, the reading operation will be explained next.

The read control circuit (hereinafter referred to as R control circuit) 43 is initialized as described later by an external initial value setting signal 5TART. The R control circuit 43 stores the address RA to be read from the bank 47.48, as will be described later.

7 address RA is counted up by at 1 t' in response to a read request signal RREQ, which will be described later. The read address signal RAM is a signal of bits excluding the lower one bit when the address RA is represented by two bits, and is outputted from the R control circuit 43 to the signal line 99. The circuit 43 also stores the number M of data that has not yet been read out of the written data. The number M is determined as follows every time the write permission signal WE becomes II 1 g.
That is, each time one piece of data is written, the count is incremented by 91'', and the second external device that receives the read permission signal ROK, for example, the read request signal input from the pipeline operation unit 1 via the signal line 15. Each time RREΩ reaches 111 #l, that is, each time one piece of data is read, it is counted down by II II II.If M is 1 or more (unread data is written to banks 47 and 48) only when the data is written to the bank for which the mode designation signal SW designates the read mode, the R control circuit 43 sends the data to the external device via the signal line 13. sr 1 #l is output as signal ROK.Whether this data is written to bank 47 or bank 48?

The least significant bit of the binary read address RA is N O
It is detected if II is 1+1 #F.

The read address signal RAH on signal line 99 is.

It is applied to the selectors 451 and 452 described above, and is applied from the selectors 451 and 452 to the address terminals AT of banks 47 and 48 depending on whether the mode designation signal SW is 0" or II II II. That is, the signal SW is 110 tr.
At this time, the odd bank 48 is in the read mode, and the read address signal RAH is sent via the selector 452.
is output to the odd bank 48. When the signal SW is "1", the even bank 47 is in the read mode, and the read address signal RAH is output to the even bank 47 via the selector 451. In this way, the read address signal/RA is applied to the bank that is in read mode.
H is applied.

Therefore, in the bank that is in read mode,
Data to be read from the address specified by the read address signal RAH is output to the output terminal DOT.

A selection circuit 49 consisting of a selector 491 selectively outputs the output of a bank in read mode to the signal line 10. When the mode designation signal SW is '0'', the odd bank 48 is in the read mode, and the selector 491 selectively outputs the data signal DOO read from the odd bank 48 to the signal line 10.This signal is used as the read data signal RDATA. When the mode designation signal SW is 1'', the even bank 47 is in the read mode, and the data signal DO read from the even bank 47 is sent to an external device.
The selector 491 selects E and outputs it to the second external device via the signal line 10. Of course, bank 47,4
If the wiring logic is allowed for the output terminal DOT of bank 4,
7. By controlling the input of the chip select terminal and output enable terminal of 48, the data line 471 and the data line 4
The function corresponding to the selection circuit 491 can be realized by simply combining the circuits 81.

Note that the second external device, for example, a pipeline arithmetic unit, takes in the signal RDATA when the signal ROK is 1'' and it is readable.

To indicate that read data is received, the signal RREO is output as #1 #l to the R control circuit 43. The R control circuit increases the read address RA by one in the poetry cycle in which the signal RREQ is "1".

In this way, data at address 0 of even bank 47, data at address 0 of odd bank 48, data at address 1 of even bank 47, data at address 1 of odd bank 48, etc.
...and so on, starting with the oldest data written to banks 47, 48, the data is written to banks 47, 4,
The data written in 8 is read out. therefore,
The FiFO memory shown in FIG. 2 has a so-called first-in first-out memory function. In addition, as explained above, since the mode is specified independently for each bank, when data is being written to the even bank 47, it is possible to simultaneously read data written from the odd bank 48 and write the data to the even bank 47. It is possible to read the written data from the odd bank 481 and write the data to the odd bank 481 at the same time. That is, writing and reading can be performed simultaneously.

In the configuration shown in FIG. 1, since the FiFO memories 20 and 21 in FIG. 2 are used, the signals SW in the FiFO memories 20 and 21 must be synchronized. This is because in the pipeline arithmetic unit 2, the numbers of the two input data are generally always equal in the cycle in which the data is input correctly, and the signal S at 20 and 21 is
If the values of W are different, it will always be impossible to read from one FiFO memory, and since both will not be readable at the same time, no calculation will be able to start. In order to avoid this, a configuration may be adopted in which the signal SW in all FiFO memories in all devices always has the same value. For example, the sw times signal of one FiFO memory 2o is
The FO memory 21 may also be shared. In Figure 2, Fi
Regarding the FO memory 22, since there is no input to the arithmetic unit 6 other than the FiFO memory 22, synchronization regarding the signal SW is not necessary.

Next, the mode designation circuit 41, W control circuit 42, and R control circuit 43 will be explained in more detail with reference to FIGS. 3(A), 4, and 5.

The circuits 41, 42, and 43 operate with a negative phase clock signal T, and the period of this clock is the pitch of the pipeline arithmetic unit and the memory cycle time of the memory element. As shown at the bottom of Figure 6, for each cycle
The explanation will be given by numbering from 1 to 0. Each cycle is considered from the rising edge of T to the rising edge of the next T.

Unless otherwise specified, the flip-flop (hereinafter referred to as FF) and the synchronous counter (hereinafter referred to as CNT) are edge trigger types that operate at the rising edge of the clock input signal T.

The single circles at the terminals of the left and right signal lines in the figure indicate the interface signals inside the FiFO memory, and the double circles indicate the interface signals inside the FiFO memory.
Indicates that this is an interface signal with the outside of the memory.

Here, we introduce a FiF that can store up to 8 input data.
The following explanation will be given as O memory. In this configuration, each of banks 47 and 48 only needs to have a memory capacity capable of storing four pieces of data. Also, the signal line 93 for the signal WAH, the signal line 99 for the signal RAH, the signal line 57 for the signal AE. Signal A
The O signal line may also be a 2-bit address line.

Circuits 41° 42. shown in FIGS. 3(A) to 5.
43 are all synchronous circuits synchronized with the clock signal T. In the following description, the following two points are assumed. (1) Gate delay time and FF and CNT delay time clock signal T
is sufficiently small compared to the cycle time of (2) Even if the output of an FF or CNT that operates with the clock signal T is input to the next stage FF or CNT that operates with the same clock signal T, it will not malfunction.

The assumption in (2) above is that ``the value of the previous FF in one cycle determines the value of the subsequent FF in the next cycle, and the value of the previous FF in the same cycle determines the value of the subsequent FF. This means that there will be no impact. If the above assumption (1) is not satisfied.

It is necessary to calculate and consider the delay time in detail, including the banks used, and if the assumption in (2) above is not met,
It is natural that countermeasures such as making the clock signal two-phase are necessary for a synchronous circuit.

FIG. 3(A) is a circuit diagram of the mode designation circuit 41. F
The output of the inverting output terminal Q of F50 is input to the input terminal of FF50. The clock terminal of FF50 has Jf for every memory cycle, that is, every pipeline pitch.
A clock signal T of I II is applied. FF
The signal from the output terminal Q of 50 is the mode designation signal S mentioned above.
It becomes W. Now, assume that the internal state of the FF 50 is If 177. The output itO## of the terminal Q at this time is input to the input terminal. At the first rising edge of clock signal T,
FF50 takes in the output II O71 of terminal Q, and
The internal state of F50 changes from II 1 gg to 0". At this time, the output of terminal Q also changes from II O71 to #l
1 '1. Therefore, the input to the input terminal also becomes II I 11. At the second rise of the clock signal T, the FF 50 takes in the input II 1 '1 from the terminal, and the internal state of the FF 50 returns to 411 ## again. In this way, at the rising edge of the clock signal T, the FF
50(7) The internal state is “Q II, di 1, .
Turn the inversion back to green. Therefore, the output terminal Q of FF50
The signal SW, which is the output of
As mentioned above, the role of is to specify the bank's operation mode.

FIG. 3(B) shows each mode of the even bank 47 and the odd bank 48 designated by the mode designation signal SW.

Note that the mode designation circuit is as follows: (1) In order to synchronize the plurality of FiFO memories described above, one mode designation circuit may be provided and used in common.

(2) A circuit is provided to change the signal SW so that when all eight pieces of write data have arrived and there is no possibility of conflict between reading and writing on a bank, the next bank to be read can always be selected. It's okay.

FIG. 4 is a circuit diagram of the W control circuit 42.

(3) Under conditions where there is no conflict between writing and reading, a circuit may be provided to change the signal SW so that the even-oddity of the arriving data always matches the even-oddity of the bank designated for the W mode.

FIG. 4 is a circuit diagram of the W control circuit 42.

First, the roles of the CNT and FF and the functions of the main gates in FIG. 4 will be explained, and then an example of their operation will be explained according to the time chart in FIG. 6. The CNT 62 is the edge trigger type synchronous counter described above, and the number of output bits is 1 bit.

CNT64 is also an edge trigger type 3-bit synchronous counter. Terminal up is a count up instruction input terminal, terminal R is a reset terminal for clearing the contents to zero, terminal GK is an input terminal for clock terminal T, and terminal Q is an output terminal for counter contents. The count up operation is
The operation is executed when the input signal of the terminal up is in the state of "1" and the clock signal T applied to the terminal GK rises from 1'077 to "1". The input signal of terminal up is II 01
In the state ', the value of CNT remains unchanged. The FF 63 is an edge trigger type FF, and like the counter described above, the value of the output terminal Q changes at the rise of the clock signal applied to the terminal GK.

The CNT 62 is reset by an external signal 5TART, and is counted up at the end of the cycle when the external write request signal VREQ arrives (the rising edge of the clock signal T), and its output WCNT is counted up at the end of the cycle in which the external write request signal VREQ arrives (the rising edge of the clock signal T). Indicates whether the request signal 1i1REQ (write data WDATA) is for the odd bank 48 or the even bank 47. That is, "0" of the output 1i1CNT means a write request to the even bank 47, and 111 tt means a write request to the odd bank 48. Another output signal V of CNT62
The output signal of CNT is a signal of opposite polarity to that of CNT.

The CNT 64 is reset by an external signal 5TART, and is counted up at the end of a cycle in which writing to any bank is executed (a cycle in which WE is (L 11g). The output of the CNT 64 is the WA. ,
Its upper 2 bits output WAH indicate the write address of the bank, and its lower 1 bit output WAL indicates whether the write bank is even or odd. In other words, the output of CNT64 is “ooo
,” (the subscript 2 indicates a binary number. The same applies hereinafter), then
The W control circuit 42 instructs address 002 of the even bank 47 as the write destination. The output of CNT64 is “0”
012" indicates address 00. of odd bank 48, and "0102" indicates address #012g of even bank.
It indicates the address. In order to actually write in the bank, the write enable signal WE (described later) must be set to It171.
Must be.

If the signal WREO is #1 rr in a certain cycle,
The write request has arrived at the W control circuit 42 in that cycle. The data signal to be written is the signal WDATA in that cycle. That is, the corresponding signal VREQ and signal VDATA arrive at the W control 42 in the same cycle.

As shown in FIG. 3(B), in a certain cycle, the signal S
Depending on the value of W, either the even bank 47 or the odd bank 48 is designated as the W mode. On the other hand, from the outside, the W control circuit 4
Write requests arriving at 2 arrive independently of the value of signal SW. Therefore, the W control circuit 42 executes one of the following two types of write operation procedures in response to each write request that arrives.

(a) Writing to the bank is executed in the same cycle as the request arrives. A request arrives, and
When the evenness of the number of the arrived request (that is, the evenness of the write destination bank) and the evenness of the bank in the W mode state in the cycle in which the request arrived, the write operation procedure (a) is executed. Hereinafter, this will be referred to as the direct write procedure.

(b) Writing to the bank is executed in the cycle following the cycle in which the request arrived. When a certain request arrives and the evenness of the number of the arrived request does not match the evenness of the bank in the W mode state in the cycle in which the request arrived, (
The write operation procedure (b) is executed. Hereinafter, this will be referred to as delayed writing.

Exclusive OR (hereinafter referred to as FOR) gate 69 in FIG.
recognizes the mismatch between the even and odd numbers of arriving requests and the even and odd numbers of the W-mode banks. In other words, if the output of the EOR gate 69 on the signal line 88 is "0" in a certain cycle, the odds are even, and if a request arrives, a direct write procedure should be executed. Also, if the output of FOR gate 69 is II 171, there is no even-odd match and a delayed write procedure should be performed if a request arrives.

AND gates 69 and 68 recognize execution of a direct write procedure and a delayed write procedure, respectively.

The circle marked on one of the input terminals of the AND gate 69 indicates the inversion of the input signal, similar to the AND gate 441 in FIG. In other words, the output of the AND gate 69 is 1
11 tt is that the signal WREQ on the signal line 33 is IL 1 #7 and the signal on the signal line 88 is 0'''.

If the output of the AND gate 69 on the signal line 90 is ``1'', the write enable signal WE on the signal line 91 via the AO gate 70 becomes II 1 jl, and the write request to the bank is executed in the cycle in which the write request arrives. A write is performed. This is the execution of a direct write operation.

The output of the AND gate 68 on the signal line 89 is II II I
t, sr 1 n is input to the FF 63 from the terminal, and in the next cycle, the output signal +1REQDL of the FF 63 on the signal line 86 becomes it 1 tr, and the signal WE passes through the OR gate 7o to it 1 @ becomes y,
Writing in the bank is executed in the next cycle after the write request arrives. This is the execution of the delayed write procedure.

The FF 63 stores the arrival of a write request to be executed in the delayed write procedure, and instructs bank writing in the next cycle.

When the signal WE is “1”, the even bank 47 is the odd bank 4.
Writing is performed at 8. Whether the write destination bank is even or odd can be known from both the signal SW and the signal WAL. As mentioned above, in the embodiment shown in FIG. 2, the signal SW is used as an even/odd selection signal for the write destination bank.

Regarding the write instruction signal VREQ, it is considered that there are cases in which the value is transmitted as the signal WE during the cycle in which it reaches the W control circuit 42 in this way, and cases in which it is temporarily stored and transmitted as the signal WE in the next cycle. be able to. Regarding the write data signal WDTA, there are cases where its value is used directly and cases where it has to be stored until the next cycle. Signal WDATA and signal VREQ
Similarly, operations in the above two cases can be realized using two sets of AND gates (corresponding to AND gates 68 and 69), FF group (corresponding to FF63), and OR gate group (corresponding to OR gate 70). You can also do it. However, FIG. 4 shows an alternative scheme using two groups of latches.

The latches 60 and 61 are the edge trigger type F
The operation is different from F, and when the clock signal from the input terminal CK is II 1 #l, the input contents from the input terminal immediately become the output from the output terminal Q, and the clock signal changes from sr 171 to "0". When the input terminal falls, the input contents from the input terminal are held (the holding operation is called a latch operation), and the held contents are reset when the reconsideration clock signal is '0''.
It is output from the φ force terminal Q from 1 to 1 until it rises to "1".

Lunch 60 is even-numbered write data (even-numbered bank 4).
The latch 61 is used to temporarily hold the odd-numbered write data (write data to the odd-numbered bank 48). Considering the cycle in which the even-numbered write request arrives, since the signal WCNT is II 1 #l, the contents of the signal WDATA are output as they are to the output signal 5DRH of the latch 60, and when moving to the next cycle, the signal is I
When NCNT goes from HI It to It OII, the contents of the falling signal VDATA are held, and the signal 5 is also held in the next cycle.
The contents of DRH are the same as the previous cycle. In other words, in the cycle in which the even-numbered write request arrives, even-numbered bank 47
Whether the write is executed in the next cycle or the next cycle that arrives, the contents of the signal 5DRH are the correct contents of the even-numbered write data.

The latch 61 and its output signal 5DRO have the same configuration except that the clock signal to the latch 61 is the signal ICNT, and the contents of the signal 5DRO are the correct contents of the write data to the odd bank.

Next, the write operation of the FiFO memory 20 will be explained based on the operation example shown in the time chart of FIG. Arriving write requests are numbered from 0th to 7th, and are written to address 0 of even bank 47, address 0 of odd bank 48, address 1 of even bank, and up to address 3 of odd bank. be included.

Although not shown in FIG. 6, a 1'' pulse of signal 5TART prior to a series of write operations causes CNT6 to
2 and CNT64 are reset to It O71.

FF63 also connects 1''' of signal 5TART to reset terminal R.
Since the pulse of 9 is input, it is similarly reset, indicating that the first write request is an even number. In the operation example shown in Figure 6, the direct write procedure is used for write requests from 0th to 2nd. is executed, a delayed write procedure is executed for the third and fourth requests, and a direct write procedure is executed for the fifth to seventh requests.

First, the 0th write request arrives in cycle ■.

Signal WRI on signal line 33! Q and the signal wDATA on the data line 30 are input to the W control circuit 42.

That is, IREQ is sr 1 n and signal WDAT
A (7) The content is the 0th write data. In cycle ◎, the signal VCNT is still it Ot+, and the 6th
In the example shown, the signal SW is 11 O11, which indicates that the even bank is in W mode, so the FOR gate 6
The output of 7 is II O#l, the output of AND gate 68 is 10'', and the output of AND gate 90 is at 1
tp, and the output signal WE of the OR gate 70 becomes sr.
1 n. In the cycle in which the signal WE is II l #), writing is executed in the bank designated as W mode by the signal SW, as shown in FIG. That is, the signal wEE on the signal line 59 becomes "1" by the AND gate 441 in FIG. 2, and a write operation in the even bank 47 is instructed.

Next, the write address will be explained. CNT in Figure 4
After CNT64 is set by signal 5TART
The output remains “ooo,” even in cycle ■,
The signal WAH, which is the upper two bits output, is also l□Q,
71 to the address line 93. In FIG. 2, the selector 451 that determines the content of the memory address signal AE to the even bank 47 selects the write address signal WAH on the address line 93 because the signal SW is 0'', and outputs the signal WAH to the address line 57. .Through the above,
In cycle (2), the correct address 1/QQ 211 is input to the address terminal AT of the even bank 47. In the odd bank 48, the signal RAM is input to the address terminal AT by the action of the selector 452, but since the signal WEO is '0' by the action of the AND gate 442, no erroneous writing is performed.

Next, write data will be explained. In FIG. 4, in cycle 2, the signal WCNT is II 1 gH, so the latch 60 immediately transfers the signal %1DATA corresponding to the 0th request on the data line 30 to the signal 5DR on the data line 82.
Output as E. The selector 461 in FIG.
Since W is II Ou, the signal 5DRII on the data line 82
! is output to the data line 55. That is, in cycle (2), the 0th write data signal DATA is correctly input to the data input terminal DIT of the even bank 47. Second
In the illustrated embodiment, the data input terminal DIT of the odd bank 48
The 0th write data is also input to the register, but the AND gate 442 ensures that the signal WEO is ztO11, so no erroneous write is performed.

The first write request arrives in the cycle, and writing to the bank is executed during the cycle, but this differs from the cycle (2) in that the writing destination is the odd bank 48. In other words, since the signal SW is 1" in FIG. 2, the signal WEE
is II Opg, and the signal WEO is 1''.The value of the signal WAH is selected by the selector 452 and the signal AO
The value of signal 5DRO is selected by selector 461 and output as signal DIO. The value of C: NT64 of the 4mth 3 bits is as follows: When moving to the cycle ■, the signal WE is tz 1 n in the cycle ■, WCNT and wCNT are also the same, and the signal WREQ is II II II in the cycle ■, so the cycle is So each at 1
#J and It are reversed to OII. Since the output of the AND gate 68 is "0" even in cycle ■, the output WREQDI of FF63 is II OI also in cycle ■.
It remains I. The contents of the signal VDATA in the cycle ■ are held in the latch 60, and the contents of the signal VDATA in the cycle ■ are held in the latch 60.
Although it is output as DER, it is not used.

A second request arrives in cycle (2) and is written to even bank 47 during cycle (2). Since the signal WE is "1" in the cycle, the output of the CNT 64 becomes "010□" in the cycle ■, and the second write request data signal WDATA is written to the first even bank 47.

The time chart in FIG. 6 shows an example of the operation when the third write request arrives at cycle (2) instead of at cycle (2). In cycle 2, the arriving request is the odd numbered one, and the odd bank 48 is not in W mode, so in the next cycle 2, the third write request is executed in the odd bank 48. In Figure 4, in cycle ■,
The signal WCNT is II 1 '1 and the signal SW is '
0''.

Due to the action of FOR gate 67 and AND gates 68 and 69, the signal on signal line 89 becomes 411 #l, and signal line 88
The upper signal becomes PA0'''. Since #1'7 is input to the input signal terminal of the FF 63, it outputs II1 #F to the signal REQDL for the first time in the next cycle (2).

The bank write enable signal WE is rr O in cycle ■.
tz, which becomes '1'' to instruct the third write in cycle (2). This operation is the delayed write procedure described above.

The CNT 64 that creates the write address WA holds the same value "0112" from cycles ■ to ■ because WE is '0' in cycles ■ and ■.

In cycle (2), the value in the odd bank memory 48 is correct as a memory address. 01□'' is input.

Next, write data will be explained. cycle ■to 3
The th write data signal 1110ATA h<arrives. Signal 1i1CNT which becomes the clock signal of latch 61
＃～11″ for cycle ■, II 0 for cycle ■
+1, so the contents of the output signal 5DRO of the latch 61 are the same as the contents of the signal WDATA in the cycle ■ not only in the cycle ■ but also in the cycle ■.

Therefore, the write data of the third request can be correctly input to the odd bank 48 in cycle (2).

In the W control circuit 42 of FIG. 4, it is assumed that the odd-numbered link 48 cannot execute the third write request in cycle ■, but can execute it in the next cycle ■.In other words, in cycle ■, the signal SW is If it is 0''', it is predicted from the periodicity of SW that the signal SW will be It177 in the next cycle (2).

The fourth write request also arrives when the even bank 47 is not in the W mode (cycle ■), so it is written to the even bank 47 with a -cycle delay.

Since the fifth request arrives when the even bank 48 is in the W mode (cycle ■), it is immediately written to the even bank 48, like the 0th, 1st, and 2nd requests. That is, a direct write procedure is executed in which the corresponding signal 1t) IRQ and signal WE become 1'' in the same cycle (2).

Every time 8 write requests are written to the bank, the 3-bit counter CNT64 is counted up and its output increases from 000□'' to ``1112''.In cycle 10, it may return to ``ooo''. However, since the 8th write request does not arrive from the outside, even bank 47
The contents of address OO□ will not be destroyed.

FIG. 5 is a circuit diagram of the R control circuit 43. The edge trigger type counter (hereinafter referred to as CNT) 100 is a 4-bit counter that can count up and count down. The counter 100 is instructed to count up and down by inputting the count up terminal UP and the count down terminal DOWN. Input signal WE of terminal UP is at 1
t' and terminal DOWN (7) Input signal RREQ
When It Opg (71), the counter 100 counts up by it I If at the rising edge of the clock signal T input to the clock terminal CK.

Terminal UP (71 input signal WE is /l O11 TE, terminal D
OwN (7) When the input signal RREQ is #171, it similarly counts down by It 1 '1. When the re-inputs are both 110II or 1'', the counter does not count up or count down.The 4-bit output REQCNT of CNT100 is output to the four data lines 101.The value of CNT100 has been written but has not yet been counted. It shows the number of data that has not been read out.The CNT 100 is configured with a 4-bit counter so that it can store nine types of input data from 0 to 8.The CNT 100 is input to the reset terminal R. Initial value setting signal 5TART
will be reset.

The 4-bit output of the CNT 100 is input to the OVER gate 104, where each bit is inverted and the result is sent to the signal line 1.
It is output on 05. When the output of OVER gate 104 is not 0, it indicates that there is data written to banks 47, 48 that has not yet been read. CNT109 is 2
It is a 3-bit binary counter.

Initial value setting signal 5TART input to reset terminal R
is reset by the input signal R of the count up terminal UP.
When REQ is #IH', the count is incremented at the rising edge of the clock signal T input to the clock terminal GK.

The 3-bit binary value of CNT 109 indicates the read address. The CNT109 uses the upper 2 bits of the counter value as the bank read address RAH and sets it to address 899.
The lower one bit is outputted to the signal line 111 as a signal RAL indicating whether the bank to be successively output is even or odd.

112 is the bank to be read now and the mode designation signal SW
This is a FOR gate for detecting whether or not the bank matches the bank specified for reading. When the least significant bit signal RAL of the CNT 109 is a Ott, the even bank 47 is the bank to be read now, and when the signal SW is "1'", the even bank 47 is in the R mode. When the signal RAL is tz 1 tr, the odd bank 48
is the bank to be read now, and the signal SW is II.
At the time of 011, this odd bank 48 becomes the R mode.

Therefore, EOR gate 112 outputs signals RAL and S
W is tt Ou and LL I II, or II
It satisfies the condition that LL 1 $7 is output when I II and 110 II, and II OII is output at other times. AND gate 106 performs a logical product of the signals on signal lines 105 and 113. Therefore, when the read permission signal ROK, which is the output of the AND gate 106, becomes "1", there is data written in the banks 47 and 48 that has not been read yet.
And only when the condition that the bank containing the data to be read is in the read mode is satisfied. In other cases, it becomes II OII. As described above, the signal ROK is a signal that indicates that data can be read from the FiFO memory.

The operation of the R control circuit will be explained based on the operation example shown in the time chart of FIG. The read request signal RREQ input from the signal line 15 is guaranteed to be 1" only when the signal ROK is it 1 n. For example, the vibe line control logic circuit 3 in FIG. do.

Also, it is the same as W control in that CNTl00, 109 are initialized to trO# by signal 5TART prior to a series of read requests.

In cycle 2, in which the 0th write data is written to the even bank 47, the signal WE becomes II I II and CNT
100 counts up at the next rising edge of the clock signal T, and in cycle 2, its output REQCNT becomes "0001".
2'', and the OVER gate 104 outputs 111'7 to the signal line 105, indicating that unread data exists in the bank.On the other hand, in the cycle, the signal SW is I
The EOR gate 112 detects that 47 of the even bank is in the R mode and outputs 171 II to the signal line 113. The AND gate 106 determines that the two conditions are met and outputs the signal ROK as II 1
n is output onto the signal line 13.

In the example of FIG. 6, as a response to this, an external signal RREQ is sent.
is "1". When the signal RREQ on the signal line 15 is 11171, the CNT 109 is counted up. In cycle ■, since the signal WE indicating the first write becomes 111H at the same time, CNT100
does not perform counting operation. In the next cycle ■, the output signal RIEQCNT is held as "0001."
Indicates that there is one piece of data that has not been read. During the cycle, the output signal RAH of the upper two bits of the CNT 109 is rzOO#l, and is sent to the selection circuit 45 in FIG. 2 via the data line 99. In this cycle, the signal SW is "1", and the selector 4 in the selection circuit 45
51 selects signal RAH and sends it to address terminal AT of bank 47. On the other hand, AND gate 441 in FIG.
Since the signal SW is II I H, the signal WEE is tt
Set it to O#. Since the signal WEE is it On, the bank 47 executes the read operation to the 'oo' address indicated by the signal AE, and uses the contents of the 0th data written in the previous cycle as the signal DOE to read data 1/ 1A471.The selector 491 in FIG.
”, the signal DOE is selected and output as the signal RDATA to the data line 10. By the above operation, the 0th data is output to the signal RDATA during cycle (2).

The same operation is performed for reading the first and second data, except for the value of the signal SW and whether the bank used is even or odd.

The third data is written in 1. after the second data write is completed. It is executed after three more cycles.

Therefore, in the second data reading cycle (2), the signal RR[EQ is 1'1'' and the signal WE is II OI
Since CNT100 is counted down, the signal REQCNT becomes "00002" in the first cycle (■).
”, the signal ROK becomes #O$1, and the signal RRF
Q = "1" should not be input, and the read operation for the third data is not executed. In the cycle (2) following the cycle in which the signal WE becomes '1' in response to the third write request signal WREO, the signal REQCNT
becomes "00012" and the signal ROK becomes III I #l. However, the operation example in Figure 6 shows a case where the signal RREQ remains 0''' due to another external factor. In the next cycle 2, the signal SW becomes 1 and the third data is stored. Since the odd-numbered bank 48 that is currently in use is not in the R mode, the signal ROK becomes 0''. In this cycle,
The value of CNT100 is "ooio," reflecting the fourth write in the previous cycle. Next cycle■
Then, since the signal SW is II O11, the signal 110K is '
1'', and 1'' is input as the signal RREQ. In this cycle ■, the signal R11! QCNT
has increased to "0011 x".

An example is shown below in which the fourth to seventh data are read out consecutively. In cycle O, the seventh and final data is sent out as signal RDATA. During 13 cycles from cycle ① to cycle O, 8 write requests and 8 read requests are processed in this FiFO memory. In particular, during the four cycles from cycle ■ to cycle ■, four write requests and four read requests are processed in parallel, one each in each cycle, demonstrating the maximum processing capacity of this FiFO memory. .

FIG. 7 shows, as an embodiment of the present invention, the configuration of a data processing device in which a plurality of arithmetic units are dynamically coupled according to instructions from a program using the above-mentioned FiFO memory as an intermediary. This has been explained up to Figure 6.

By using the FiFO memory, even if write data is generated intermittently, a function is realized in which data is correctly transferred from one arithmetic unit to another.

Pipeline calculation units 901 and 902゜9
03 and FiFO memory 921, 922, 923°924
．． Distribution logic circuits 911 and 912 are interposed between 925 and 925 . The distribution logic circuits 911 and 912 have a function of allocating FiFO memories to the input source and output destination of each unit according to instructions from the outside. Distribution logic circuit 911, 91
2 consists of a plurality of multi-input selector groups, which are well known. For example, at a certain point, the output of the FiFO buffer 921 is input to the unit 903 to the distribution logic circuit 9.
12 is selected and the output of the unit 903 is a FiFO; the distribution logic circuit 911 can select it to be the input of the J memory 922, and at another time the FiFO memory 923 is the input of the unit 903 and the FiFO memory is the output. The 0 distribution logic circuits 911 and 912, which can be dynamically reconfigured to select 924, can be configured using a large number of selectors.

Note that the FiFO memory 921. . . . , each configuration of 925 is composed of the FiFO memory circuit 41 shown in FIG. , each FiF
O memory 921. ...-, 925.

The arithmetic unit in FIG. 7 may be not only an arithmetic unit that performs four arithmetic operations, but also a storage control unit that can store a large amount of data.

〔Effect of the invention〕

As explained above, according to the present invention, multiple arithmetic units and storage control devices that can operate simultaneously are dynamically coupled, and even if valid data is intermittently output, correct data is made available to subsequent arithmetic units. It is possible to provide a data processing device that inputs the data as data to a subsequent arithmetic unit.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional pipeline processing unit to which FiFO memory is applied, Figure 2 is a block diagram of FiFO memory used in the present invention, and Figure 3 (A) shows the bank operation mode. A circuit diagram showing an example of a mode specifying circuit, FIG. 3(B) is a diagram showing the mode of each bank specified by the specifying signal Sw, and FIG. 4 is an example of a W# control circuit that controls bank writing. 5 is a circuit diagram showing an example of an R control circuit that controls bank reading, FIG. 6 is a time chart for explaining the operation of the FiFO memory, and FIG. FIG. 1 is a block diagram of a pipeline type data processing device according to an embodiment. 41...Mode designation circuit, 47...Even bank, 4
8... Odd bank, 100... Write/read control circuit. Fig. S 6 Row 1-+

Claims (1)

[Scope of Claims] 1. Storage means having storage locations that are sequentially designated for storing data, a plurality of calculation means that execute calculations on inputs and provide outputs corresponding to the calculation results, and the storage selection means for selectively connecting said storage means to said plurality of calculation means such that data from said calculation means is given as input to said calculation means and data output from said calculation means is sequentially given to said storage means; , the storage means is controlled to sequentially read data to the selected arithmetic means, the presence of data to be read from the storage means is detected, and the data is read from the storage means when the data does not exist. 1. A data processing device comprising: successive control means for prohibiting operations. 2. The data processing device according to claim 1, further comprising write control means for controlling the storage means so as to sequentially write data outputs of one selected calculation means into the storage means. . 3. The succession control means detects the existence of data in the storage means by detecting a difference between the number of data written in the storage means and the number of data read from the storage means. The first claim characterized in that
3. The data processing device according to item 1 or 2.