JPS5481740A - Composite computer unit - Google Patents

Composite computer unit

Info

Publication number
JPS5481740A
JPS5481740A JP14878177A JP14878177A JPS5481740A JP S5481740 A JPS5481740 A JP S5481740A JP 14878177 A JP14878177 A JP 14878177A JP 14878177 A JP14878177 A JP 14878177A JP S5481740 A JPS5481740 A JP S5481740A
Authority
JP
Japan
Prior art keywords
computers
interfaces
bus
computer
reception
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14878177A
Other languages
Japanese (ja)
Other versions
JPS6020778B2 (en
Inventor
Tadahiro Yanagisawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP52148781A priority Critical patent/JPS6020778B2/en
Publication of JPS5481740A publication Critical patent/JPS5481740A/en
Publication of JPS6020778B2 publication Critical patent/JPS6020778B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE: To give the same input as that for the computer in use to the standby computer in the complex computer system, in which computers are connected among themseleves by duplexed buses, so that turbulance in control, which is liable to occur during switching-over of computers, can be prevented.
CONSTITUTION: The system provides a plurality of computers 1A, 1B, 2 and 3, system buses 5A and 5B tying the computers 1A and 1B to the computers 2 and 3, system bus interfaces 4A and 4B connecting the computers 1A, 1B, 2 and 3 to the bus 5A and 5B, system bus transmission interfaces 8A and 8B, and system bus reception interfaces 9A and 9B. The transmission interfaces 8A and 8B are provided with the bus driver 91 and the buffer circuit 82, and the bus driver 91 and the reception control circuit 43 are placed in the reception interfaces 9A and 9B. Further, the interfaces 8A, 8B, 9A and 9B are duplicated, giving the same input to the computers 2 or 3 during waiting as the computer 3 or 2 in usage.
COPYRIGHT: (C)1979,JPO&Japio
JP52148781A 1977-12-13 1977-12-13 Composite computer equipment Expired JPS6020778B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52148781A JPS6020778B2 (en) 1977-12-13 1977-12-13 Composite computer equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52148781A JPS6020778B2 (en) 1977-12-13 1977-12-13 Composite computer equipment

Publications (2)

Publication Number Publication Date
JPS5481740A true JPS5481740A (en) 1979-06-29
JPS6020778B2 JPS6020778B2 (en) 1985-05-23

Family

ID=15460522

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52148781A Expired JPS6020778B2 (en) 1977-12-13 1977-12-13 Composite computer equipment

Country Status (1)

Country Link
JP (1) JPS6020778B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117943A (en) * 1983-11-14 1985-06-25 タンデム　コンピユーターズ　インコーポレーテツド Communication controller system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117943A (en) * 1983-11-14 1985-06-25 タンデム　コンピユーターズ　インコーポレーテツド Communication controller system

Also Published As

Publication number Publication date
JPS6020778B2 (en) 1985-05-23

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