JPS57178533A - Data transmission controlling interface with memory - Google Patents

Data transmission controlling interface with memory

Info

Publication number
JPS57178533A
JPS57178533A JP56062485A JP6248581A JPS57178533A JP S57178533 A JPS57178533 A JP S57178533A JP 56062485 A JP56062485 A JP 56062485A JP 6248581 A JP6248581 A JP 6248581A JP S57178533 A JPS57178533 A JP S57178533A
Authority
JP
Japan
Prior art keywords
data
software
buffer
memory
transmission controlling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56062485A
Other languages
Japanese (ja)
Inventor
Isao Miyazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56062485A priority Critical patent/JPS57178533A/en
Publication of JPS57178533A publication Critical patent/JPS57178533A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Computer And Data Communications (AREA)

Abstract

PURPOSE:To reduce a load on the software of a system by eliminating the need for character-by-character read/write control by software by incorporating a memory in a data transmission controlling interface. CONSTITUTION:An input and output controller 1 is connected to an address bus line, and a memory buffer 5 with about 1K-byte capacity is connected to a data bus line. To the controller 1 and buffer 5, a transmission controlling register 2 connected to a transmitting data line and a reception controlling register 3 connected to a receiving data line are connected, respectively, thus constituting a data transmission controlling interface. For transmission, data is set in the buffer 5 through software and the data in the buffer 5 is transmitted through hardware. For reception, data read in the register 3 is set in the buffer 5 through the hardware, and the data is read through the software, thereby reducing a load on the software of this system.
JP56062485A 1981-04-27 1981-04-27 Data transmission controlling interface with memory Pending JPS57178533A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56062485A JPS57178533A (en) 1981-04-27 1981-04-27 Data transmission controlling interface with memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56062485A JPS57178533A (en) 1981-04-27 1981-04-27 Data transmission controlling interface with memory

Publications (1)

Publication Number Publication Date
JPS57178533A true JPS57178533A (en) 1982-11-02

Family

ID=13201522

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56062485A Pending JPS57178533A (en) 1981-04-27 1981-04-27 Data transmission controlling interface with memory

Country Status (1)

Country Link
JP (1) JPS57178533A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59189438A (en) * 1983-04-12 1984-10-27 Chino Works Ltd Signal processing circuit
JPH05134952A (en) * 1991-05-27 1993-06-01 Fujitsu Ltd Data transfer system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59189438A (en) * 1983-04-12 1984-10-27 Chino Works Ltd Signal processing circuit
JPH05134952A (en) * 1991-05-27 1993-06-01 Fujitsu Ltd Data transfer system

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