JPS57164330A - Input and output interface device - Google Patents

Input and output interface device

Info

Publication number
JPS57164330A
JPS57164330A JP4860181A JP4860181A JPS57164330A JP S57164330 A JPS57164330 A JP S57164330A JP 4860181 A JP4860181 A JP 4860181A JP 4860181 A JP4860181 A JP 4860181A JP S57164330 A JPS57164330 A JP S57164330A
Authority
JP
Japan
Prior art keywords
input
data
output controller
driver
receiver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4860181A
Other languages
Japanese (ja)
Other versions
JPS6028025B2 (en
Inventor
Joji Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4860181A priority Critical patent/JPS6028025B2/en
Publication of JPS57164330A publication Critical patent/JPS57164330A/en
Publication of JPS6028025B2 publication Critical patent/JPS6028025B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To achieve high speed data transfer, by providing a means giving a buffer storing data transferred between an input/output controller and an input/ output device and transferring the data of the buffer to the input/output controller with the start from the input/output controller. CONSTITUTION:A driver 44 provided in an input/output controller 4' is connected to a receiver 91 having an AND function provided in a data cash device 9 via a data cash tag effective line 10 in 1 bit. An output bus/tag bus 6 and the like are connected to the receiver 91 and a driver 92 is connected to an input bus and the like 8. The receiver 91 and the driver 92 are connected to a buffer storing data provided in the data cash device 9 similarly, i.e., to a memory 93.
JP4860181A 1981-03-31 1981-03-31 Input/output interface device Expired JPS6028025B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4860181A JPS6028025B2 (en) 1981-03-31 1981-03-31 Input/output interface device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4860181A JPS6028025B2 (en) 1981-03-31 1981-03-31 Input/output interface device

Publications (2)

Publication Number Publication Date
JPS57164330A true JPS57164330A (en) 1982-10-08
JPS6028025B2 JPS6028025B2 (en) 1985-07-02

Family

ID=12807921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4860181A Expired JPS6028025B2 (en) 1981-03-31 1981-03-31 Input/output interface device

Country Status (1)

Country Link
JP (1) JPS6028025B2 (en)

Also Published As

Publication number Publication date
JPS6028025B2 (en) 1985-07-02

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