JPS6437652A - Data input system - Google Patents

Data input system

Info

Publication number
JPS6437652A
JPS6437652A JP19396587A JP19396587A JPS6437652A JP S6437652 A JPS6437652 A JP S6437652A JP 19396587 A JP19396587 A JP 19396587A JP 19396587 A JP19396587 A JP 19396587A JP S6437652 A JPS6437652 A JP S6437652A
Authority
JP
Japan
Prior art keywords
data
memory
input device
bus
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19396587A
Other languages
Japanese (ja)
Inventor
Shinji Ogata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP19396587A priority Critical patent/JPS6437652A/en
Publication of JPS6437652A publication Critical patent/JPS6437652A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To speed up data input by transferring data directly from an input device to a main memory only by a writing sequence. CONSTITUTION:A data bus 5 connected from an adaptor 14 to a data memory 2b is disconnected from a processor 1 by a bus separating means 15. Then, a writing strobe signal 7 in a writing sequence to the data memory 2b used for the processor 1 is temporarily suspended by an AND gate circuit 13 and the adaptor 14 receives data from the input device 3 by the signal 7 and sends the data to the data bus 5. Simultaneously with the sending of the data, the AND gate circuit 13 is controlled to make the signal 7 effective and the data inputted from the input device 3 and sent to the data bus 5 are written in the memory 2b. Consequently, the data can be directly inputted from the input device 3 to the data memory 2b only by the writing sequence of the processor 1.
JP19396587A 1987-08-03 1987-08-03 Data input system Pending JPS6437652A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19396587A JPS6437652A (en) 1987-08-03 1987-08-03 Data input system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19396587A JPS6437652A (en) 1987-08-03 1987-08-03 Data input system

Publications (1)

Publication Number Publication Date
JPS6437652A true JPS6437652A (en) 1989-02-08

Family

ID=16316711

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19396587A Pending JPS6437652A (en) 1987-08-03 1987-08-03 Data input system

Country Status (1)

Country Link
JP (1) JPS6437652A (en)

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