JPS55105729A - Data processing unit - Google Patents

Data processing unit

Info

Publication number
JPS55105729A
JPS55105729A JP1218079A JP1218079A JPS55105729A JP S55105729 A JPS55105729 A JP S55105729A JP 1218079 A JP1218079 A JP 1218079A JP 1218079 A JP1218079 A JP 1218079A JP S55105729 A JPS55105729 A JP S55105729A
Authority
JP
Japan
Prior art keywords
peripheral units
cpu2
transmission channel
data transmission
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1218079A
Other languages
Japanese (ja)
Inventor
Fusao Funaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1218079A priority Critical patent/JPS55105729A/en
Publication of JPS55105729A publication Critical patent/JPS55105729A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable the date transfer between peripheral units without exclusive use of CPU, by providing the data transmission channel between the peripheral units controlled with CPU for input and output operation.
CONSTITUTION: The unit provides the main memory unit 1, CPU2, peripheral units 3 and 4, and data transmission channel 5 enabling the data transfer between the peripheral units 3 and 4. The data transmission channel 5 is connected with the peripheral units 3, 4 through the data line 7 and status line 8 and with the CPU2 through the input and output line 13. The data transmission channel 5 is started with the instruction from CPU2 and data transfer is started. The data transmission channel controls the data transfer between the peripheral units 3 and 4 without via the main memory unit 1 without the instruction of CPU2 when start is made once from CPU2.
COPYRIGHT: (C)1980,JPO&Japio
JP1218079A 1979-02-07 1979-02-07 Data processing unit Pending JPS55105729A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1218079A JPS55105729A (en) 1979-02-07 1979-02-07 Data processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1218079A JPS55105729A (en) 1979-02-07 1979-02-07 Data processing unit

Publications (1)

Publication Number Publication Date
JPS55105729A true JPS55105729A (en) 1980-08-13

Family

ID=11798218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1218079A Pending JPS55105729A (en) 1979-02-07 1979-02-07 Data processing unit

Country Status (1)

Country Link
JP (1) JPS55105729A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57166658A (en) * 1981-04-06 1982-10-14 Hitachi Ltd Auxiliary storage device
JPS585823A (en) * 1981-07-03 1983-01-13 Fujitsu Ltd Channel processing device
JPS6039265A (en) * 1983-08-12 1985-03-01 Fujitsu Ltd Data transfer system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57166658A (en) * 1981-04-06 1982-10-14 Hitachi Ltd Auxiliary storage device
JPS585823A (en) * 1981-07-03 1983-01-13 Fujitsu Ltd Channel processing device
JPS6039265A (en) * 1983-08-12 1985-03-01 Fujitsu Ltd Data transfer system

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