JPS5679347A - Control device equipped with hierarchical common memory - Google Patents
Control device equipped with hierarchical common memoryInfo
- Publication number
- JPS5679347A JPS5679347A JP15418379A JP15418379A JPS5679347A JP S5679347 A JPS5679347 A JP S5679347A JP 15418379 A JP15418379 A JP 15418379A JP 15418379 A JP15418379 A JP 15418379A JP S5679347 A JPS5679347 A JP S5679347A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- input
- high speed
- control device
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Multi Processors (AREA)
Abstract
PURPOSE: To make it unnecessary to use a large capacity memory for the high speed control memory, by having in common a low speed large capacity memory, and transferring only the microprogram required for each input/output operation to the high speed control memory.
CONSTITUTION: The input/output instructions from the channel of CPU16a or 16b are informed to the high speed processor 12a or 12b. The processor 12a or 12b initializes the control device 30a or 30b in response to start of the input processing by this input instruction, by the microprogram on the high speed control memory 10a or 10b. Subsequently, the processing program corresponding to the input/output device 18a or 18b according to this start is requested to the memory control part 24. In response to this request, the control part 24 transfers the block of this processing program to the memory 10a or 10b of the control device which is a request origin, from the main memory 26 of low speed large capacity. In this way, only if only the program required for the low rank device is input to the memory 10a or 10b, it is enough, and therefore it is unnecessary to make the memory capacity of the memory 10a or 10b so large.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15418379A JPS5679347A (en) | 1979-11-30 | 1979-11-30 | Control device equipped with hierarchical common memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15418379A JPS5679347A (en) | 1979-11-30 | 1979-11-30 | Control device equipped with hierarchical common memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5679347A true JPS5679347A (en) | 1981-06-29 |
Family
ID=15578642
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15418379A Pending JPS5679347A (en) | 1979-11-30 | 1979-11-30 | Control device equipped with hierarchical common memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5679347A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5924335A (en) * | 1982-07-31 | 1984-02-08 | Fujitsu Ltd | Information processing system |
-
1979
- 1979-11-30 JP JP15418379A patent/JPS5679347A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5924335A (en) * | 1982-07-31 | 1984-02-08 | Fujitsu Ltd | Information processing system |
JPH0381182B2 (en) * | 1982-07-31 | 1991-12-27 | Fujitsu Ltd |
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