JPS57206974A - Shared memory control circuit - Google Patents

Shared memory control circuit

Info

Publication number
JPS57206974A
JPS57206974A JP9079681A JP9079681A JPS57206974A JP S57206974 A JPS57206974 A JP S57206974A JP 9079681 A JP9079681 A JP 9079681A JP 9079681 A JP9079681 A JP 9079681A JP S57206974 A JPS57206974 A JP S57206974A
Authority
JP
Japan
Prior art keywords
memory
access
given
processor
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9079681A
Other languages
Japanese (ja)
Inventor
Eitaro Konii
Masayuki Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Heavy Industries Ltd
Original Assignee
Sumitomo Heavy Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Heavy Industries Ltd filed Critical Sumitomo Heavy Industries Ltd
Priority to JP9079681A priority Critical patent/JPS57206974A/en
Publication of JPS57206974A publication Critical patent/JPS57206974A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To ensure a smooth process, by connecting a memory to a processor that delivered an access request as long as no access is given to the memory and keeping the processor waiting when an access is given to the memory. CONSTITUTION:A processing system includes the 1st and 2nd processors 11 and 12 plus a memory part 13 which is used in common by both processors 11 and 12. An input selecting circuit 18 receives a request to a memory 14 from at least one of the processors 11 and 12 and connects the memory 14 to the processor that gave an access request as long as no access is given to the memory 14. While a waiting request signal is given to the processor that delivered an access request signal incase an access is given to the memory 14 at a moment when the access request signal is received.
JP9079681A 1981-06-15 1981-06-15 Shared memory control circuit Pending JPS57206974A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9079681A JPS57206974A (en) 1981-06-15 1981-06-15 Shared memory control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9079681A JPS57206974A (en) 1981-06-15 1981-06-15 Shared memory control circuit

Publications (1)

Publication Number Publication Date
JPS57206974A true JPS57206974A (en) 1982-12-18

Family

ID=14008541

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9079681A Pending JPS57206974A (en) 1981-06-15 1981-06-15 Shared memory control circuit

Country Status (1)

Country Link
JP (1) JPS57206974A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6478358A (en) * 1987-09-19 1989-03-23 Canon Kk Data communication system
JPH01142855A (en) * 1987-11-30 1989-06-05 Mitsubishi Electric Corp Memory access device
JPH01281556A (en) * 1988-05-09 1989-11-13 Fujitsu Ltd Access control circuit for dual port ram

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6478358A (en) * 1987-09-19 1989-03-23 Canon Kk Data communication system
JPH01142855A (en) * 1987-11-30 1989-06-05 Mitsubishi Electric Corp Memory access device
JPH01281556A (en) * 1988-05-09 1989-11-13 Fujitsu Ltd Access control circuit for dual port ram

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