JPS5685168A - Access control system for main storage - Google Patents

Access control system for main storage

Info

Publication number
JPS5685168A
JPS5685168A JP16185279A JP16185279A JPS5685168A JP S5685168 A JPS5685168 A JP S5685168A JP 16185279 A JP16185279 A JP 16185279A JP 16185279 A JP16185279 A JP 16185279A JP S5685168 A JPS5685168 A JP S5685168A
Authority
JP
Japan
Prior art keywords
line
address
block fetch
given
main storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16185279A
Other languages
Japanese (ja)
Inventor
Mikio Ito
Takashi Chiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16185279A priority Critical patent/JPS5685168A/en
Publication of JPS5685168A publication Critical patent/JPS5685168A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent the CPU and others from being set under the waiting state by the block fetch given from a buffer storage, by securing an automatic block fetch for the address next to the line which started the block fetch.
CONSTITUTION: When a block fetch (BF) request is given to the main storage (MS)50, an examination is given whether the line of the address next to the line which started the BF exists on the buffer storage (BS). When the absence of the line becomes clear, the next signal showing the necessity of the next address line is sent to the MS control part (MCU)51. Receiving this signal, the MCU51 adds the prescribed value not only to the line required by the MS request of the BF but to the address, and then performs the BF for the line of the next address.
COPYRIGHT: (C)1981,JPO&Japio
JP16185279A 1979-12-13 1979-12-13 Access control system for main storage Pending JPS5685168A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16185279A JPS5685168A (en) 1979-12-13 1979-12-13 Access control system for main storage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16185279A JPS5685168A (en) 1979-12-13 1979-12-13 Access control system for main storage

Publications (1)

Publication Number Publication Date
JPS5685168A true JPS5685168A (en) 1981-07-11

Family

ID=15743163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16185279A Pending JPS5685168A (en) 1979-12-13 1979-12-13 Access control system for main storage

Country Status (1)

Country Link
JP (1) JPS5685168A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0668736B2 (en) * 1986-01-29 1994-08-31 ディジタル エクイプメント コ−ポレ−ション Apparatus and method for providing a cache memory unit with a write operation utilizing two system clock cycles
US6341334B1 (en) 1998-03-24 2002-01-22 Mitsubishi Denki Kabushiki Kaisha Bridge method, bus bridge, and multiprocessor system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0668736B2 (en) * 1986-01-29 1994-08-31 ディジタル エクイプメント コ−ポレ−ション Apparatus and method for providing a cache memory unit with a write operation utilizing two system clock cycles
US6341334B1 (en) 1998-03-24 2002-01-22 Mitsubishi Denki Kabushiki Kaisha Bridge method, bus bridge, and multiprocessor system

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