JPS56114023A - Transfer control system - Google Patents

Transfer control system

Info

Publication number
JPS56114023A
JPS56114023A JP1654580A JP1654580A JPS56114023A JP S56114023 A JPS56114023 A JP S56114023A JP 1654580 A JP1654580 A JP 1654580A JP 1654580 A JP1654580 A JP 1654580A JP S56114023 A JPS56114023 A JP S56114023A
Authority
JP
Japan
Prior art keywords
transfer
ccw
control
control part
interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1654580A
Other languages
Japanese (ja)
Other versions
JPS6019815B2 (en
Inventor
Kishio Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55016545A priority Critical patent/JPS6019815B2/en
Publication of JPS56114023A publication Critical patent/JPS56114023A/en
Publication of JPS6019815B2 publication Critical patent/JPS6019815B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Abstract

PURPOSE:To reduce the soft overhead, by giving no interruption to the processor as long as the transfer process is normal and at the same time carrying out a connection process for the transfer indication word by a transfer device. CONSTITUTION:When the process start instruction is received from the processor, the connection display word QCW monitor part 31 is started to monitor the transfer indication word CCW of the QCW. Then the CCW analysis part 32 starts when the CCW has a number excepting O. Thus an analysis is carried out to shift the control to the transfer control part 33, and a data transfer is carried out via the bus 16. If the transfer complets in the normal state, the control shifts to the connection control part 34 from the transfer control part 33. The control shifts to the interruption control part 35 only when a fault is detected while the transfer is under operation. In such way, no interruption is given to the processor while the transfer process is normal. Furthermore the connection process of the CCW is carried out by a transfer device. As a result, the soft overhead can be reduced.
JP55016545A 1980-02-15 1980-02-15 Transfer control method Expired JPS6019815B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55016545A JPS6019815B2 (en) 1980-02-15 1980-02-15 Transfer control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55016545A JPS6019815B2 (en) 1980-02-15 1980-02-15 Transfer control method

Publications (2)

Publication Number Publication Date
JPS56114023A true JPS56114023A (en) 1981-09-08
JPS6019815B2 JPS6019815B2 (en) 1985-05-18

Family

ID=11919226

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55016545A Expired JPS6019815B2 (en) 1980-02-15 1980-02-15 Transfer control method

Country Status (1)

Country Link
JP (1) JPS6019815B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988007238A1 (en) * 1987-03-17 1988-09-22 Fanuc Ltd High-speed floating point operation system
JPH0277848A (en) * 1988-06-10 1990-03-16 Nec Corp Microcomputer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988007238A1 (en) * 1987-03-17 1988-09-22 Fanuc Ltd High-speed floating point operation system
JPH0277848A (en) * 1988-06-10 1990-03-16 Nec Corp Microcomputer

Also Published As

Publication number Publication date
JPS6019815B2 (en) 1985-05-18

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