JPS5745628A - Data transfer controlling system - Google Patents

Data transfer controlling system

Info

Publication number
JPS5745628A
JPS5745628A JP11992380A JP11992380A JPS5745628A JP S5745628 A JPS5745628 A JP S5745628A JP 11992380 A JP11992380 A JP 11992380A JP 11992380 A JP11992380 A JP 11992380A JP S5745628 A JPS5745628 A JP S5745628A
Authority
JP
Japan
Prior art keywords
connection display
display word
transfer
section
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11992380A
Other languages
Japanese (ja)
Inventor
Kishio Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11992380A priority Critical patent/JPS5745628A/en
Publication of JPS5745628A publication Critical patent/JPS5745628A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To enable priority control in response to the content of transferred processing, by performing execution control according to a plurality of connection display word group displaying the connecting stage of a data transfer indicating word and the priority level. CONSTITUTION:When a processing start instruction 47 is received from a processor, the execution controlling section 41 of a connection display word is started and a level 1-connection display word address is stored. When the 2nd processing start instruction is received from the processor, the section 41 displays ''level 2 is under start'' and a level 2-connection display word address is stored. After that, control is transferred to a connection display word analysis section 42 and a transfer controlling section 43 to perform data transfer according to the connection display word. If the transfer operation is normally finished, the control is transferred from the section 43 to a connection controlling section 14 and also to an interruption controlling section 45 only when a failure is detected. Thus, while ''data is under transfer'' is performed normally, no interruption is caused and the priority control according to the content of transfer processing is made possible.
JP11992380A 1980-08-30 1980-08-30 Data transfer controlling system Pending JPS5745628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11992380A JPS5745628A (en) 1980-08-30 1980-08-30 Data transfer controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11992380A JPS5745628A (en) 1980-08-30 1980-08-30 Data transfer controlling system

Publications (1)

Publication Number Publication Date
JPS5745628A true JPS5745628A (en) 1982-03-15

Family

ID=14773516

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11992380A Pending JPS5745628A (en) 1980-08-30 1980-08-30 Data transfer controlling system

Country Status (1)

Country Link
JP (1) JPS5745628A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6149270A (en) * 1984-08-16 1986-03-11 Fuji Electric Co Ltd Input/output control system of multiprocessor
JPS61156352A (en) * 1984-12-27 1986-07-16 Fujitsu Ltd Control system for instruction queue

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6149270A (en) * 1984-08-16 1986-03-11 Fuji Electric Co Ltd Input/output control system of multiprocessor
JPS61156352A (en) * 1984-12-27 1986-07-16 Fujitsu Ltd Control system for instruction queue
JPH049349B2 (en) * 1984-12-27 1992-02-19

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