JPS54144839A - Test unit for data processing unit - Google Patents

Test unit for data processing unit

Info

Publication number
JPS54144839A
JPS54144839A JP5353778A JP5353778A JPS54144839A JP S54144839 A JPS54144839 A JP S54144839A JP 5353778 A JP5353778 A JP 5353778A JP 5353778 A JP5353778 A JP 5353778A JP S54144839 A JPS54144839 A JP S54144839A
Authority
JP
Japan
Prior art keywords
signal
bus
control
address
setter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5353778A
Other languages
Japanese (ja)
Inventor
Kenji Ogaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5353778A priority Critical patent/JPS54144839A/en
Publication of JPS54144839A publication Critical patent/JPS54144839A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Electric Properties And Detecting Electric Faults (AREA)

Abstract

PURPOSE: To display the signal condition without interruption of CPU operation, by providing the address setter, control setter, coincidence circuit, registers and display unit, and by making display while storing the signal coincident with the content of the setter and the signal on the bus.
CONSTITUTION: The signal exchange between CPU, memory MM, and I/O is made via the address bus A, data bus D and control bus C. This system is provided with the address setter ADS, and control setter CTS, where the switches S1 to S4 performing the set of control condition corresponding to the control signal are provided. The coincidence between the content of the control condition by the switches S1 to S4 and the control signal on the bus C, and that between the content of address designation set at ADS and the address designation signal on the bus A are detected with the coincidence detection circuit ADT. The output drives the register RG, stores the signal on the bus D to RG when the detected output is caused, and the content is displayed on the data display unit DAD. Further, the signal on the bus A detected with the circuit ADT is displayed on the address display unit ADD to effectively perform the test and confirmation.
COPYRIGHT: (C)1979,JPO&Japio
JP5353778A 1978-05-04 1978-05-04 Test unit for data processing unit Pending JPS54144839A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5353778A JPS54144839A (en) 1978-05-04 1978-05-04 Test unit for data processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5353778A JPS54144839A (en) 1978-05-04 1978-05-04 Test unit for data processing unit

Publications (1)

Publication Number Publication Date
JPS54144839A true JPS54144839A (en) 1979-11-12

Family

ID=12945548

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5353778A Pending JPS54144839A (en) 1978-05-04 1978-05-04 Test unit for data processing unit

Country Status (1)

Country Link
JP (1) JPS54144839A (en)

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