JPS57123460A - Hardware monitor system - Google Patents
Hardware monitor systemInfo
- Publication number
- JPS57123460A JPS57123460A JP56007979A JP797981A JPS57123460A JP S57123460 A JPS57123460 A JP S57123460A JP 56007979 A JP56007979 A JP 56007979A JP 797981 A JP797981 A JP 797981A JP S57123460 A JPS57123460 A JP S57123460A
- Authority
- JP
- Japan
- Prior art keywords
- hardware
- latch
- memory
- hardware monitor
- microinstruction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3089—Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
PURPOSE:To realize various types of hardware monitores without using a patch board, by incorporating a microinstruction (group) into a routine of a microprogram of a process to be monitored in order to set and reset a hardware monitoring latch. CONSTITUTION:An information processor 100 includes a control memory 5, a read data register 6 for the memory 5, a decoder circuit 7 and a process unit 9. A latch 8 exclusive for hardware monitor which is set and reset by a microinstruction is provided to the processor 100. The contents of the latch 8 is supplied to a hardware monitor device 300 via a signal line 106 and in the form of a signal to be observed. The read/write is possible for the memory 5 from a maintenance device 400 through a signal line 101.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56007979A JPS57123460A (en) | 1981-01-23 | 1981-01-23 | Hardware monitor system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56007979A JPS57123460A (en) | 1981-01-23 | 1981-01-23 | Hardware monitor system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57123460A true JPS57123460A (en) | 1982-07-31 |
Family
ID=11680559
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56007979A Pending JPS57123460A (en) | 1981-01-23 | 1981-01-23 | Hardware monitor system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57123460A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10290608B2 (en) | 2016-09-13 | 2019-05-14 | Allegro Microsystems, Llc | Signal isolator having bidirectional diagnostic signal exchange |
US11115244B2 (en) | 2019-09-17 | 2021-09-07 | Allegro Microsystems, Llc | Signal isolator with three state data transmission |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5347352B1 (en) * | 1970-09-10 | 1978-12-20 |
-
1981
- 1981-01-23 JP JP56007979A patent/JPS57123460A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5347352B1 (en) * | 1970-09-10 | 1978-12-20 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10290608B2 (en) | 2016-09-13 | 2019-05-14 | Allegro Microsystems, Llc | Signal isolator having bidirectional diagnostic signal exchange |
US10651147B2 (en) | 2016-09-13 | 2020-05-12 | Allegro Microsystems, Llc | Signal isolator having bidirectional communication between die |
US11115244B2 (en) | 2019-09-17 | 2021-09-07 | Allegro Microsystems, Llc | Signal isolator with three state data transmission |
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