JPS6149270A - Input/output control system of multiprocessor - Google Patents

Abstract

PURPOSE:To adjust a using quantity of an input output device with a simple processing by comparing the number of an input output request commands actually preserved with the allowable number set concerning CPU, which is the transmission original of the input output request command. CONSTITUTION:Plural central processing devices CPU1-CPUn and one input output device 10 are connected through a common bus 11 and an input output control circuit 12. Respective VPU is composed of main memories PM1-PMn and processors P1-Pn and a common memory 9 is installed at a common bus 11. When the input output control circuit 12 receives an input output request command which respective CPU transmit while a program is executed, a waiting line allowable number for preserving an input output request command set for every CPU beforehand and an awaiting line number preserved presently are compared, and it is determined by the comparing result whether the received input output request command can be accepted or not.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for controlling input/output request commands in a multiprocessor system consisting of a plurality of central processing units interconnected by a common bus.

[Conventional technology]

Multiple central processing units (CPs) connected by a common bus
In a multiprocessor system consisting of U),
Generally, since input/output request commands are randomly generated from each CPU to a shared input/output device, a plurality of input/output request commands may overlap at the same time. In such a case, a method is known in which only the input/output request commands are temporarily stored in a queue, and input/output processing operations are executed in order from the first received command. The memory that temporarily holds input/output request commands in this way is placed in the input/output control device or on a shared memory, but the input/output request commands that must be stored in a queue are If the number exceeds the storage capacity of the memory, the reception will not store new I/O request commands until the actual I/O operation progresses and there is at least one free space in the queue. It becomes impossible. Therefore, the CPU that sent the input/output request command that was not accepted will wait until the input/output request command is accepted by the input/output control device.

[Problem that the invention seeks to solve]

Conventionally, all input/output request commands generated by each CPU are treated equally from the perspective of the input/output control device.
It is fine if the contents and processing purposes of the tasks (programs) assigned to each CPU are the same, but if they are different, for example, a program with a high degree of urgency is primarily executed by the CPU, and a program with a low degree of urgency is executed by CPU2. When this is done, the following disadvantages arise:

(1) Since input/output request commands for processing programs with low urgency are also stored in the memory in a queue, there is no room in the queue. Therefore, input/output request commands for processing highly urgent programs may not be received.

(2) Since input/output operations are always performed on a first-come, first-served basis, priority processing is impossible even if program processing has priority. Note that there is generally no special relationship between the frequency of occurrence of input/output request commands transmitted during program execution and the urgency of program execution.

[Problem that the invention seeks to solve]

The following two methods are known as countermeasures to solve the above-mentioned drawbacks.

First, the first method is to provide an input/output request command reception memory for each CPU in the input/output control device, create a queue for input/output request commands for each CPU, and then wait from the queue of the CPU with a high priority. Actual input/output processing is performed sequentially.

However, such a method has the disadvantage that the memory of the input/output control device increases, its control becomes complicated, and the cost of the device increases.

Next, as a second method, priority information is added to the input/output request command, and the input/output control device sorts the queue of input/output requests based on the priority information. After sorting the items in the order of the items, the actual input/output processing operations are performed. However, in this method, each time there is an input/output request, the priorities of all input/output request commands in the queue are compared with each other, and as a result of the comparison,
It becomes necessary to change the order of the queue, increasing the load on the input/output control device. Furthermore, since there is a limit to the storage capacity for holding input/output request commands, there is a drawback that once the queue is full, subsequent input/output request commands cannot be processed.

[Purpose of the invention]

The purpose of the present invention is to solve the above-mentioned drawbacks of the prior art, and by an extremely simple process,
An object of the present invention is to provide an input/output control method that allows the usage of shared input/output equipment to be adjusted for each central processing unit according to program urgency and processing assigned to each central processing unit.

[Failure to solve the problem]

The present invention is based on the number of queues permissible for each CPU, that is, the maximum number of input/output request commands that can be held (limit value ) in the input/output control device, and each time the input/output control device receives an input/output request command, it will check the number of actually held input/output request commands and the source of the input/output request command. It is compared with the allowable number set for the CPU to determine whether or not to allow acceptance of the input/output request command.

[Effect]

With this configuration, it is possible to adjust the amount of shared input/output equipment used for each CPU according to the urgency of the program assigned to each CPU and the processing coal (program execution frequency). As a result, efficient operation of the multiprocessor system is achieved. In particular, each CPU
This becomes even more noticeable when the objectives of the work (programs) assigned to each program become different and diversified.

〔Example〕

Embodiments of the present invention shown in the drawings will be described in detail below.

FIG. 1 shows a plurality of central processing units CPU, , CPU2.・
...CPUn and one input/output device (Ilo) 10
This shows a multiprocessor system in which these are connected via a common bus 11 and an input/output control circuit (10C) 12. Each CPU has a main memory PM.

PM2. ...PMn and processor device P+,
Pz.

...Pn, and the common bus 11 has a common memory (CM) common to this system.
9 is provided.

2 and 3 are input/output control circuits 1 schematically shown to explain the operation of the input/output control circuit shown in FIG. 1.
The configuration of No. 2 is shown below. In FIG. 2, 13 is a counter device that uses, for example, a predetermined area of a memory as a counter, and each counter 13-+, 13-z, .
” 13-n are CPUs, respectively.

CPU, . . . Corresponding to CP Un, each stored value N.

~Nn is a permissible number (limit value) indicating how many input/output request command queues each CPU can hold. For example, as for the CPU, as shown in the block of counter 13-I, up to four input/output request commands can be held. Similarly, there are two and three for CPU2 and CPUn, respectively.

14 is a link terminal (QL) for holding received input/output request command data (input/output direction, number of input/output data, input/output data address, etc.) in a storage block as a queue, and 15 is a queue. The number of received input/output request command data currently held as QN (=
The reception is a storage unit that stores the number of blocks in the queue (the number of blocks in the queue), and in the figure, the block (Ri) 1 of input/output request command data
．． Block (Rii)2. Block (Riii) 3 of 3
It is shown that the items are linked. Note that this data block l, 2.3 is CPU U + ~CP
It was sent from one of the Un and has already been accepted. Further, 16 indicates a link terminal (EL) for empty storage blocks, and 17 indicates a storage unit that stores the current number EN of empty storage blocks. storage block (
Ei)4. This shows that there are two blocks (Eii) 5. Here, when the input/output request command data Ri is processed, the value of QN changes to 2 and the value of EN changes to 3.

In the multiprocessor system of the present invention, each CPU
Input/output request data from the CPU is transmitted and received via an input/output control register (not shown) assigned to an address that can be referenced from each CPU.

In addition, input/output request data is sent to the DM via the common bus 11.
Transfer is performed in a known manner such as A (direct memory access) method, but since these do not directly relate to the essence of the present invention, the invention will be omitted.

Referring again to FIG. 2, the actual input/output processing operation of the input/output control circuit 12 is being executed based on the input/output request command data Ri located at the head of the queue, and the processing of the data Ri is being performed. Until the process is completed, it is possible to receive two more input/output request command data.

In such a state, when the input/output control circuit 12 receives a new input/output request command from the CPUt, for example, the contents of the counter 13-2 corresponding to CPUZ, that is, N2=2, and the number of blocks in the queue The contents of QN, ie, 3, are compared.

In this case, since the number of blocks in the queue exceeds the allowable number preset for the CPU 2, the new input/output request command cannot be accepted and the CPU is notified of this fact. Also, for example, a new input/output request command R is sent from the CPU.
If Y is received, the contents of the counter 13-0 corresponding to the CPU, ie, N=4, and the contents of the number of blocks QN in the queue, ie, QN=3, as described above.
are compared, but the number of blocks in the queue is
Since the number is below the preset allowable number (limit number) for It is linked to the end of the queue as a waiting block (RY) 6, and input/output request command data RY is registered. In this way, the number of actually linked blocks increases by one, and the QNO value becomes 4, as shown in FIG. On the other hand, the number of free blocks decreases by one, so the ENO value becomes one.

In this way, even if there are empty blocks that can hold input/output request commands, some CPUs may not be able to accept the input/output request commands they have issued, depending on the allowable number set in advance for each CPU. As a result, the usage amount of the input/output device 10 shared by each CPU is adjusted according to the allowable number.

In other words, c p' u with a high priority can use many input/output devices.

Here, the allowable number N1 to Nn for each CPU is often set when designing a multiprocessor system, but it can also be set while the multiprocessor system is running, and it is also possible to change this. .

In the embodiments described above, the configuration shown in FIG. 2 has been described as being provided in the input/output control circuit, but it can also be provided in the common memory 9 shown in FIG.

Further, the input/output control circuit only needs to have the function of either an input control circuit or an output control circuit, and may be a so-called input or output control circuit.

〔Effect of the invention〕

The present invention provides a system for each CP constituting a multiprocessor system.
When the input/output control circuit receives an input/output request command sent by U during program execution, the permissible number of queues for holding input/output request commands (limit value) set in advance for each CPU.
The number of queues currently held is compared with the number of queues currently held, and based on the comparison result it is decided whether or not to accept the received input/output request command. Therefore, the usage amount for each CPU of the input/output equipment shared in the multiprocessor system. is very easily adjusted.

Therefore, the usage of input/output devices can be set in accordance with the urgency and processing amount of work assigned to each of the plurality of CPUs, and the usage can be controlled in an efficient manner. Therefore, there is no need to wait too long or something with a low level of urgency is ignored.

Moreover, this control can be realized through simple processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a multiprocessor system according to the present invention, and FIGS. 2 and 3 are block diagrams schematically showing the configuration and operation within an input/output control circuit. cpu... Central processing unit 10... Input/output device 12... Input/output control circuit 13... Counter mW 14.16... Link terminal patent applicant
Fuji Electric Seizo Co., Ltd. Same as above Fuji Facom Control Co., Ltd. Agent: Tetsuya Mori, patent attorney: Yoshiaki Naito, patent attorney. Agent Patent Attorney 'IW Mizu Authorized Agent Patent Attorney Nobu Kajiyama Figure 1

Claims (1)

[Claims] In a multiprocessor system in which a plurality of central processing units and an input or output control device shared by the central processing units are connected by a common bus, the input or output control device corresponds to each of the central processing units, It has a limit value for the number of queues that can be accepted, and when an input/output request command is received from the central processing unit, it is the number of queues currently held and the source of the input/output request command. An input/output control method for a multiprocessor system, characterized in that the number of queues is compared with a limit value set for the central processing unit, and when the limit value is not exceeded, input/output commands are sequentially held as a queue. .