JPS5723131A - Acquisition system for priority right of interruption - Google Patents

Acquisition system for priority right of interruption

Info

Publication number
JPS5723131A
JPS5723131A JP9824380A JP9824380A JPS5723131A JP S5723131 A JPS5723131 A JP S5723131A JP 9824380 A JP9824380 A JP 9824380A JP 9824380 A JP9824380 A JP 9824380A JP S5723131 A JPS5723131 A JP S5723131A
Authority
JP
Japan
Prior art keywords
interruption
priority
pulse
bus
acquisition system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9824380A
Other languages
Japanese (ja)
Inventor
Hiroshi Nagase
Takao Ueno
Kazuhiro Hiraide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP9824380A priority Critical patent/JPS5723131A/en
Publication of JPS5723131A publication Critical patent/JPS5723131A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To permit one processor to attain access without conflicting with other requesting origins, by giving a priority to only one of interruption requests generated simultaneously and by rejecting other interruption requests. CONSTITUTION:Once an interruption request pulse 5i is inputted to a circuit Si, an inhibiting gate 1 connecting with a signal line 11 indicating the state of an interruption priority acquisition bus 4 permits the pulse 5i on an interruption request line 12 to pass through it, and sets a flip-flop (FF) 2. As the FF2 is set, a bus driver 3 is driven to set a ''1'' which shows that the interruption priority acquisition bus 4 is in use, and the inhibition gate 1 is closed. If a call conflicts, the FF2 is set at the same time and when the following processing becomes abnormal, all FFs are reset.
JP9824380A 1980-07-18 1980-07-18 Acquisition system for priority right of interruption Pending JPS5723131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9824380A JPS5723131A (en) 1980-07-18 1980-07-18 Acquisition system for priority right of interruption

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9824380A JPS5723131A (en) 1980-07-18 1980-07-18 Acquisition system for priority right of interruption

Publications (1)

Publication Number Publication Date
JPS5723131A true JPS5723131A (en) 1982-02-06

Family

ID=14214513

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9824380A Pending JPS5723131A (en) 1980-07-18 1980-07-18 Acquisition system for priority right of interruption

Country Status (1)

Country Link
JP (1) JPS5723131A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0114485A2 (en) * 1982-12-21 1984-08-01 Texas Instruments Incorporated Communications system and device therefor employing control line minimization
EP0130000A2 (en) * 1983-06-23 1985-01-02 Northern Telecom Limited Apparatus and method for controlling access by a plurality of units to a shared facility

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0114485A2 (en) * 1982-12-21 1984-08-01 Texas Instruments Incorporated Communications system and device therefor employing control line minimization
EP0130000A2 (en) * 1983-06-23 1985-01-02 Northern Telecom Limited Apparatus and method for controlling access by a plurality of units to a shared facility
EP0130000A3 (en) * 1983-06-23 1985-09-18 Northern Telecom Limited Apparatus and method for controlling access by a plurality of units to a shared facility

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