JPS5723133A - Priority interruption system - Google Patents
Priority interruption systemInfo
- Publication number
- JPS5723133A JPS5723133A JP9824580A JP9824580A JPS5723133A JP S5723133 A JPS5723133 A JP S5723133A JP 9824580 A JP9824580 A JP 9824580A JP 9824580 A JP9824580 A JP 9824580A JP S5723133 A JPS5723133 A JP S5723133A
- Authority
- JP
- Japan
- Prior art keywords
- interruption
- gate
- circuit
- bus
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
- G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Small-Scale Networks (AREA)
Abstract
PURPOSE:To reduce a processing load by providing an interruption requesting circuit with a counter synchronized among circuits and by permitting a circuit having made an interruption request to inform a processor of its address independently. CONSTITUTION:A timing indicating circuit 25 generates a strobe signal for a gate 21 every time the contents of a counter 13 coincide with a given address 10 characteristic to a corresponding interface device (IF). An interruption pulse generated in the IF sets a flip-flop (FF)16 to be inputted to the gate 21. The input gate 21 of an interruption bus control circuit 26 turns on only when their two signals are present and no interruption signal is present on an interruption display bus 101, thereby setting an FF17. At this time, the interruption signal is sent onto the interruption display bus 101 via a buffer 22 and at the same time, it is also sent onto its address bus 102 via a gate 20. The figure shows an interruption control part by 2, a block interruption part by 4, and a processor by 3.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9824580A JPS5723133A (en) | 1980-07-18 | 1980-07-18 | Priority interruption system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9824580A JPS5723133A (en) | 1980-07-18 | 1980-07-18 | Priority interruption system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5723133A true JPS5723133A (en) | 1982-02-06 |
Family
ID=14214567
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9824580A Pending JPS5723133A (en) | 1980-07-18 | 1980-07-18 | Priority interruption system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5723133A (en) |
-
1980
- 1980-07-18 JP JP9824580A patent/JPS5723133A/en active Pending
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