JPS6467664A - Information processor - Google Patents

Abstract

PURPOSE:To attain a high-speed processing by executing an access with using another bus to be used by a device, whose bus transferring quantity is comparatively small, when there are a lot of cases that a traffic is high and the other device, which desires to use the same bus, is caused to be waited. CONSTITUTION:A data transferring from an input and output control device 4 to a main storage 3 is executed via an interface bus 6 and the data transferring from central processing units 1 and 2 to the main storage 3 is executed via an interface bus 7. Here, for example, when the bus transferring quantity of the central processing unit 2 is increased and the traffic quantity of the interface bus 7 is over the prescribed traffic quantity, the central processing unit 1 detect it by a bus determining circuit 32 of a bus control circuit 22. Then, an interface control part 23 is made effective and an interface control part 24 is made ineffective. Thus, when the data are transferred to the main storage 3, the central processing unit 1 can use the interface bus 6 to be used by the input and output control device 4 whose bus transferring quantity is comparatively small.