JPS5679322A - Bus selection system - Google Patents

Bus selection system

Info

Publication number
JPS5679322A
JPS5679322A JP15615979A JP15615979A JPS5679322A JP S5679322 A JPS5679322 A JP S5679322A JP 15615979 A JP15615979 A JP 15615979A JP 15615979 A JP15615979 A JP 15615979A JP S5679322 A JPS5679322 A JP S5679322A
Authority
JP
Japan
Prior art keywords
processor
request
input
processors
detects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15615979A
Other languages
Japanese (ja)
Inventor
Kazumasa Okawa
Yuji Hirokawa
Rikio Nishida
Hiroshi Inagaki
Yoshifumi Koda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP15615979A priority Critical patent/JPS5679322A/en
Publication of JPS5679322A publication Critical patent/JPS5679322A/en
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE: To offer respective processor services equally by facilitating the contention among processors by looking in the detection of whether a request exists, by attaining access to the processor indicated by the value of a sequential counter under microprogram control.
CONSTITUTION: To input-output device 20, #0 processor 10 and #1 processor 11 are connected and service requests from processors 10 and 11 are inputted to request detecting circuit 21 via start request signal lines 31 and 32. The transmission and reception of data to and from device 20 are performed via input-output bus lines 33 and 34 connected to bus circuit 22. In addition, sequential counter 23 selecting processor 10 or 11 is made by microcontrol part 24 to count up and request detecting circuit 21 detects a start request, on the basis of the value of counter 23, by the processor number and according to whether the start request signal exists. The signal that this request detecting circut 21 detects is supplied to input-output device 26 via control part 24 to accept the start of bus circuit 22.
COPYRIGHT: (C)1981,JPO&Japio
JP15615979A 1979-11-30 1979-11-30 Bus selection system Pending JPS5679322A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15615979A JPS5679322A (en) 1979-11-30 1979-11-30 Bus selection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15615979A JPS5679322A (en) 1979-11-30 1979-11-30 Bus selection system

Publications (1)

Publication Number Publication Date
JPS5679322A true JPS5679322A (en) 1981-06-29

Family

ID=15621631

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15615979A Pending JPS5679322A (en) 1979-11-30 1979-11-30 Bus selection system

Country Status (1)

Country Link
JP (1) JPS5679322A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04140876A (en) * 1990-10-02 1992-05-14 Nec Corp Data processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04140876A (en) * 1990-10-02 1992-05-14 Nec Corp Data processing system

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