JPS5642829A - Input/output control system - Google Patents

Input/output control system

Info

Publication number
JPS5642829A
JPS5642829A JP11890879A JP11890879A JPS5642829A JP S5642829 A JPS5642829 A JP S5642829A JP 11890879 A JP11890879 A JP 11890879A JP 11890879 A JP11890879 A JP 11890879A JP S5642829 A JPS5642829 A JP S5642829A
Authority
JP
Japan
Prior art keywords
input
scanning
process request
scanner
cpu1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11890879A
Other languages
Japanese (ja)
Inventor
Yoichi Sakai
Akira Kaiyama
Tomoki Omiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP11890879A priority Critical patent/JPS5642829A/en
Publication of JPS5642829A publication Critical patent/JPS5642829A/en
Pending legal-status Critical Current

Links

Landscapes

  • Exchange Systems With Centralized Control (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE: To increase the scanning velocity of the scanner and then ensure a quick detection of the input/output device having process request for the input/output control system incorporating the scanner which detects the process request to plural numbers of the telephone, the data terminal and others.
CONSTITUTION: The process requests given from the input/output devices A1WAn and detected by the control circuit consisting of the scanning counter 2, the gate circuit 8 and FF3 each are transmitted to the CPU1. Then the CPU1 stops the scanning until it becomes possible to accept the next process request or stops the scanning for the first time when the CPU1 is not possible to accept the process request in case the next process request is detected. As a result, the scanning velocity can be increased for the scanner, and the devices A1WAn having the process requests can be detected in a short time.
COPYRIGHT: (C)1981,JPO&Japio
JP11890879A 1979-09-17 1979-09-17 Input/output control system Pending JPS5642829A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11890879A JPS5642829A (en) 1979-09-17 1979-09-17 Input/output control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11890879A JPS5642829A (en) 1979-09-17 1979-09-17 Input/output control system

Publications (1)

Publication Number Publication Date
JPS5642829A true JPS5642829A (en) 1981-04-21

Family

ID=14748137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11890879A Pending JPS5642829A (en) 1979-09-17 1979-09-17 Input/output control system

Country Status (1)

Country Link
JP (1) JPS5642829A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6174049A (en) * 1984-09-19 1986-04-16 Hitachi Ltd Request selection method
JPH04302035A (en) * 1991-03-29 1992-10-26 Nec Corp Interruption controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6174049A (en) * 1984-09-19 1986-04-16 Hitachi Ltd Request selection method
JPH04302035A (en) * 1991-03-29 1992-10-26 Nec Corp Interruption controller

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