JPS56147224A - Information processor - Google Patents

Information processor

Info

Publication number
JPS56147224A
JPS56147224A JP5124780A JP5124780A JPS56147224A JP S56147224 A JPS56147224 A JP S56147224A JP 5124780 A JP5124780 A JP 5124780A JP 5124780 A JP5124780 A JP 5124780A JP S56147224 A JPS56147224 A JP S56147224A
Authority
JP
Japan
Prior art keywords
bus
request
register
controlling part
busses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5124780A
Other languages
Japanese (ja)
Inventor
Hiroto Katsumata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5124780A priority Critical patent/JPS56147224A/en
Publication of JPS56147224A publication Critical patent/JPS56147224A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To prevent the dead lock phenomenon of the system bus and the internal bus, by providing a register for communication, which is used by both busses, and a control circuit, which processes the contention of both busses, in the bus interface unit. CONSTITUTION:Register 22 for communication can be accessed from the side of system bus 1 as well as the side of internal bus 12. In case of the access request from the side of bus 1 to register 22, the access request is accepted through bus interface SBI21 by register access controlling part 23. Controlling part 23 confirms that the access request from other parts is not present, and controlling part 23 controls address multiplexer MUX24 to make the address from bus 1 effective. MUX24 reads out contents of the request address from register 22 and supplies it to bus 1 through SBI21. In case of simultaneous access requests from busses 1 and 12, controlling part 23 keeps the request of bus 12 waiting and processes the request of bus 12 after the processing for the request of bus 1.
JP5124780A 1980-04-18 1980-04-18 Information processor Pending JPS56147224A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5124780A JPS56147224A (en) 1980-04-18 1980-04-18 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5124780A JPS56147224A (en) 1980-04-18 1980-04-18 Information processor

Publications (1)

Publication Number Publication Date
JPS56147224A true JPS56147224A (en) 1981-11-16

Family

ID=12881616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5124780A Pending JPS56147224A (en) 1980-04-18 1980-04-18 Information processor

Country Status (1)

Country Link
JP (1) JPS56147224A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984001450A1 (en) * 1982-09-30 1984-04-12 Western Electric Co Deadlock detection and resolution scheme
JPS6438858A (en) * 1987-08-05 1989-02-09 Fujitsu Ltd Competition preventing interface circuit
JPH01205365A (en) * 1988-02-12 1989-08-17 Nec Corp Bus acquisition control system
JPH04260956A (en) * 1990-09-03 1992-09-16 Internatl Business Mach Corp <Ibm> Method for avoiding deadlock
JPH076124A (en) * 1993-01-29 1995-01-10 Internatl Business Mach Corp <Ibm> System and method for transfer of information
EP1049022A2 (en) * 1999-04-28 2000-11-02 Tenovis GmbH & Co. KG Bus system and client for such bus system

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984001450A1 (en) * 1982-09-30 1984-04-12 Western Electric Co Deadlock detection and resolution scheme
EP0113163A1 (en) * 1982-09-30 1984-07-11 Western Electric Company, Incorporated Deadlock detection and resolution scheme
JPS6438858A (en) * 1987-08-05 1989-02-09 Fujitsu Ltd Competition preventing interface circuit
JPH01205365A (en) * 1988-02-12 1989-08-17 Nec Corp Bus acquisition control system
JPH04260956A (en) * 1990-09-03 1992-09-16 Internatl Business Mach Corp <Ibm> Method for avoiding deadlock
JPH076124A (en) * 1993-01-29 1995-01-10 Internatl Business Mach Corp <Ibm> System and method for transfer of information
EP1049022A2 (en) * 1999-04-28 2000-11-02 Tenovis GmbH & Co. KG Bus system and client for such bus system
EP1049022A3 (en) * 1999-04-28 2006-04-12 Tenovis GmbH & Co. KG Bus system and client for such bus system

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