JPS5489434A - Memory access control processing system - Google Patents

Memory access control processing system

Info

Publication number
JPS5489434A
JPS5489434A JP15822177A JP15822177A JPS5489434A JP S5489434 A JPS5489434 A JP S5489434A JP 15822177 A JP15822177 A JP 15822177A JP 15822177 A JP15822177 A JP 15822177A JP S5489434 A JPS5489434 A JP S5489434A
Authority
JP
Japan
Prior art keywords
fetch
store
request
issued
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15822177A
Other languages
Japanese (ja)
Inventor
Kazunari Hatanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15822177A priority Critical patent/JPS5489434A/en
Publication of JPS5489434A publication Critical patent/JPS5489434A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Abstract

PURPOSE:To make the data transfer processing efficient by accepting the next store signal after completion of the end signal corresponding to the fetch only when store follows fetch in respect to two memory access requests. CONSTITUTION:When a fetch request from channel unit 8-0 is first issued and a store request from unit 8-1 is next issued, a memory end signal is issued from the main memory side to access request processing circuit 10 corresponding to this first fetch and is transferred onto data buffer 9. Next, data corresponding to the store request is temporarily stored in buffer 9 and is transferred to the main memory. In case of store-store, store-fetch and fetch-fetch except this combination, the priority processing is performed only by judgement of circuit 10, and the second request is accepted without waiting for the processing of the first access in respect to two access requests which occurred in order. As a result, it is possible to process data transfer with a high efficiency.
JP15822177A 1977-12-27 1977-12-27 Memory access control processing system Pending JPS5489434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15822177A JPS5489434A (en) 1977-12-27 1977-12-27 Memory access control processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15822177A JPS5489434A (en) 1977-12-27 1977-12-27 Memory access control processing system

Publications (1)

Publication Number Publication Date
JPS5489434A true JPS5489434A (en) 1979-07-16

Family

ID=15666921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15822177A Pending JPS5489434A (en) 1977-12-27 1977-12-27 Memory access control processing system

Country Status (1)

Country Link
JP (1) JPS5489434A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60123944A (en) * 1983-12-07 1985-07-02 Fujitsu Ltd Buffer memory controlling system of information processor
JPS6120154A (en) * 1984-07-06 1986-01-28 Nec Corp Memory access control device
JPS6120153A (en) * 1984-07-06 1986-01-28 Nec Corp Memory access control device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60123944A (en) * 1983-12-07 1985-07-02 Fujitsu Ltd Buffer memory controlling system of information processor
JPH0526216B2 (en) * 1983-12-07 1993-04-15 Fujitsu Ltd
JPS6120154A (en) * 1984-07-06 1986-01-28 Nec Corp Memory access control device
JPS6120153A (en) * 1984-07-06 1986-01-28 Nec Corp Memory access control device

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