JPS54144136A - Lsi output control system - Google Patents

Lsi output control system

Info

Publication number
JPS54144136A
JPS54144136A JP5313578A JP5313578A JPS54144136A JP S54144136 A JPS54144136 A JP S54144136A JP 5313578 A JP5313578 A JP 5313578A JP 5313578 A JP5313578 A JP 5313578A JP S54144136 A JPS54144136 A JP S54144136A
Authority
JP
Japan
Prior art keywords
ram
lsi
address
content
reduce
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5313578A
Other languages
Japanese (ja)
Other versions
JPS628810B2 (en
Inventor
Tosaku Nakanishi
Toshio Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP5313578A priority Critical patent/JPS54144136A/en
Publication of JPS54144136A publication Critical patent/JPS54144136A/en
Publication of JPS628810B2 publication Critical patent/JPS628810B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To reduce the adverse effect given to the peripheral unit, by performing the replacement processing of the content of the buffer register for peropheral control in a short time similarly as the incorporated RAM bit processing.
CONSTITUTION: In the unit providing the LSI of ROM-RAM system and the peripheral unit controlled with the output of LSI, the buffer registers 3, 4 for liquid crystal display unit control are placed at a part of area of RAM incorporated in LSI. Further, RAM is provided with the address decoders 1, 2, the decoder 2 decodes the address and selects the data, the content of the registers 3, 4 is made time-sharing process with the time sharing signals H1' to H4' to output to the segment buffers 5, 6 via the lines xi to yi. Further, the decoders 1, 2, are constituted so that arbitrary address can be designated with the instruction from ROM similar to the other RAM area(operational use) to reduce the effect to the display unit.
COPYRIGHT: (C)1979,JPO&Japio
JP5313578A 1978-04-28 1978-04-28 Lsi output control system Granted JPS54144136A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5313578A JPS54144136A (en) 1978-04-28 1978-04-28 Lsi output control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5313578A JPS54144136A (en) 1978-04-28 1978-04-28 Lsi output control system

Publications (2)

Publication Number Publication Date
JPS54144136A true JPS54144136A (en) 1979-11-10
JPS628810B2 JPS628810B2 (en) 1987-02-25

Family

ID=12934369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5313578A Granted JPS54144136A (en) 1978-04-28 1978-04-28 Lsi output control system

Country Status (1)

Country Link
JP (1) JPS54144136A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51142233A (en) * 1975-04-07 1976-12-07 Texas Instruments Inc Digital indicator
JPS5279833A (en) * 1975-12-26 1977-07-05 Casio Comput Co Ltd Display system
JPS52155939A (en) * 1976-06-21 1977-12-24 Hitachi Ltd Control system for micro program

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51142233A (en) * 1975-04-07 1976-12-07 Texas Instruments Inc Digital indicator
JPS5279833A (en) * 1975-12-26 1977-07-05 Casio Comput Co Ltd Display system
JPS52155939A (en) * 1976-06-21 1977-12-24 Hitachi Ltd Control system for micro program

Also Published As

Publication number Publication date
JPS628810B2 (en) 1987-02-25

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