JPS628810B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention provides a ROM-RAM type control circuit (LSI
etc.) and a peripheral device connected to the control circuit and controlled based on the output from the control circuit, in particular, a buffer register for controlling the peripheral device is connected to the control circuit. It can be provided at the same level address as the built-in RAM, and the content setting, content conversion, etc. of the buffer register can be controlled by the same control method as the control of the content setting, content conversion, etc. of the above-mentioned built-in RAM. The present invention provides an output control method that makes it possible to

The present invention will be described in detail below, taking as an example a device (for example, an electronic clock, an electronic desk calculator with a clock, an electronic desk calculator, etc.) that includes an LSI as a control circuit and a liquid crystal display device as a peripheral device.

Conventionally, when controlling a liquid crystal display device with an LSI, W registers Wa ₁ , Wa ₂ ,..., as shown in Fig. 1 are used.
It has Wb ₄ , and the RAM is
The contents were transferred to the W register as is (or after arithmetic processing) and output. FIG. 1 is a block diagram showing only the main parts of a 1/4 duty liquid crystal drive. Further, FIG. 2 is a diagram showing a one-digit segment configuration of the display section, and FIG. 3 is a diagram showing the connection state of each electrode. A liquid crystal display device having a configuration as shown in FIGS. 2 and 3 is well known.

The contents of the random access memory RAM are addressed by address registers BM, BL and retrieved into buffer register W via accumulator AC. The data is input to the buffer register W while being shifted one bit at a time. The buffer register W has the number of bits equal to the number of display digits. For example, information on a segment to be lit at the timing of _H1 (that is, information on a segment related to the _H1 line) is stored in the buffer register _Wa1. ，
When entering Wb ₁ , the 1st bit of Wa ₁ corresponds to the segment at the intersection of H ₁ and a ₁ in Figure 3, and the 2nd bit of Wa 1 corresponds to the segment at the intersection of H 1 and a ₁ in Figure 3.
The th bit corresponds to the segment at the intersection of _H1 and _a2 .

When all data from RAM is transferred to Wa ₁ and Wa ₂ , the contents of Wa ₁ are transferred to Wa ₂ , and the contents of Wb ₁ are transferred to Wa 2.
The segment information that should be moved to Wb ₂ and lit at the timing of H ₂ is transferred from RAM to the accumulator.
Transferred to Wa ₁ and Wb ₁ via AC.

By repeating the above operations, Wa ₄ will have segment information related to the H ₁ line, Wa ₃ and Wb ₃ will have segment information related to the H ₂ line, and Wa ₂ and Wb ₂ will have segment information related to the H 2 line.
The segment information related to _H3 line is Wa ₁ ,
Wb ₁ stores segment information related to the H ₄ line. Then, it is selected by the signals H ₁ to _{H 4} applied to the output gate GATE, is converted into a predetermined voltage waveform via the voltage waveform converter VC, and the voltage is supplied to the display body DSP.

The above is an example of a conventional liquid crystal display device control method. In this method, if you try to replace only arbitrary digits of data (for example, in the case of a clock's time display, counter display, etc.), All buffer registers had to be moved and all contents replaced. In particular, in a liquid crystal display device, the time required to replace register contents has a large effect on display flickering, so this time must be made as short as possible.

The present invention has been made in view of the above points, and in the case of a peripheral device such as a liquid crystal display device, buffer registers corresponding to all digits and segments are the same as the built-in RAM of a control circuit (LSI, etc.). The present invention provides an output control method which is provided at the address of the buffer register so that "transfer between RAMs" and "processing of RAM bits" can be performed in exactly the same way for this buffer register. With this configuration, processing for exchanging the contents of the buffer register can be performed in a short period of time in the same way as processing RAM bits, thereby minimizing negative effects on peripheral devices such as display flickering. be able to.

Examples will be described below.

FIG. 4 is a block diagram showing the configuration of one embodiment of the present invention. In this embodiment, the present invention is implemented in a 1/4 duty liquid crystal driving system.

In the figure, numerals 3 and 4 are buffer registers for controlling the liquid crystal display device, and correspond to buffer registers Wa ₁ , Wa ₂ , . . . , Wb ₄ of the conventional example. However, in this embodiment, the buffer registers 3 and 4 are
The feature is that it is provided in a part of the LSI built-in RAM. One digit worth of segment information is stored in 8 bits per horizontal row. For example, the portion 7 in the figure stores the segment information of the fifth digit from the top of the display. Note that a, b, . . . , h in FIG. 4 correspond to a, b, . . . , h in FIG. 2. With this configuration, if you want to change the display content of any digit, simply specify the address of the part that stores the information of the relevant digit and change only the 8 bits of that part. Only one digit will be displayed on the display.

This will be explained in more detail below.

In FIG. 4, 1 and 2 are RAM address decoders, respectively. Further, 2 selects data at the same time as decoding the address. In address decoder 2, Min ₁ to ₄
is the input data to buffer registers 3 and 4 (4
Mout ₁ to ₄ are output data (4 bits)
It is. 3 and 4 are LSIs, respectively, as mentioned above.
In the example shown in Fig. 4, the contents are time-divided by time-division signals H ₁ ' to H ₄ ', and are divided into lines xi and yi. From there, it is output to segment buffers 5 and 6. Buffers 5 and 6 are voltage waveform converters and are needed only when driving a liquid crystal display device.

The operation will be explained below.

Address decoders 1 and 2 address buffer registers 3 and 4 in the same way as other RAM areas, and can specify arbitrary addresses by instructions from the ROM. When transferring data directly from another RAM area (for calculations) to buffers 3 and 4, one digit at a time is transferred via an accumulator (4 bits for a 4-bit machine, 4 bits for an 8-bit machine (8 bits) in sequence. In the case of replacing just one arbitrary bit or one digit, this can be accomplished by using a bit set or bit reset command for a specified address, or by using a swap command with an accumulator.

In either case, the total time from the start of processing to the end of processing is not much different from the conventional method, but
In any case, the method of the present invention is superior in that the processing time for exchanging information only for individual digits and segments is shorter.

In the above embodiment, the buffer register for controlling the liquid crystal display device is provided in a part of the built-in RAM of the LSI. An independent RAM that can be controlled may also be provided.

Furthermore, a RAM area that is part of the RAM for calculations and is not needed during display may be used as the buffer register.

As explained in detail above, according to the output control method of the present invention, when exchanging the contents of the buffer register, the buffer register can be addressed for each digit of the segment format display means, and this address can be stored in the built-in Since the address processing is the same as RAM address processing, it is sufficient to change only the contents of each display segment of a specific digit, and it is possible to prevent display flickering caused by the processing time of the above changes, and to maintain stable display and display quality. This will no longer cause a decline.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a conventional system, Fig. 2 is a diagram showing a single-digit segment configuration of a liquid crystal display device, which is a peripheral device, and Fig. 3 is a diagram showing the structure of a single-digit segment of a liquid crystal display device, which is a peripheral device. FIG. 4, which shows the connection state, is a block diagram showing the configuration of an embodiment of the present invention. Codes 1 and 2: address decoders, 3 and 4: buffer registers.

Claims (1)

[Scope of Claims] 1. A ROM-
In the output control method, a RAM type control circuit is provided, and the display signal is output to the display means via a buffer register connected to the display means and storing the display signal output from the control circuit. The register is built in the control circuit above.
It is at the same level as the RAM and is addressable for each digit of the display means, and stores display information for each digit of the display means separately for each segment in an area corresponding to each address, The content setting, content change, etc. of the buffer register is controlled by the same control method as the content setting, content change, etc. of the built-in RAM, and the content of the buffer register is output to the display means. An output control method characterized by the following.