JPS5844551A - Data writing control system - Google Patents

Abstract

PURPOSE:To decrease the number of times of writing to a memory, by adding the data part overflowed from a data bus output as a part of an address signal and delivering it to an address bus. CONSTITUTION:An address bus 3 has a margin of 2 bits to transfer an address bus A1 of 14 bits; while a data bus 4 has a shortage of 2 bits to transfer the data (d) and D2 of 10 bits. In this connection, a data in which the address A1 is set at an upper part with lower 2 bits is produced at a register 7 of 16 bits. At the same time, a data in which a data part 4 of 2 bits in the data (d) and 2D is set at the lower part with the upper part set at 0 is produced at a register 8. The data of these registers 7 and 8 are added to each other with index to synthesize address A of 16 bits and the data (d) at a register 9. The address A and the (d) of the register 9 are fed in the form of an address 10. The address 10 is separated into the address A and the data (d). On the other hand, the data D is integrated to a data input of a memory from a register 11 in the form of a data D12.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a computer system in which data with a number of bits greater than the number of bits of a data bus can be simultaneously stored in a single address specification by additionally using empty bit lines of an address bus. -Relates to a data write control method that allows data to be transferred and written to memory.

Conventionally, in microcomputer systems that use a data bus, a method has been adopted in which data that is longer than the data width of the data bus, that is, the number of bits, is written into memory in two or more times. . However, when data is transferred to an input/output device that has time constraints, there is a problem in that performance deteriorates, such as a reduction in screen rewriting speed due to CRT display memory.

On the other hand, when the micro combinator system technology uses a memory with a small storage capacity and there is a surplus in the number of digits in the address, the surplus address bit line in the address bus is used to transfer control information, etc. Sometimes things are done.

However, in this case, this is only possible by separating the extra address bit lines from the microprocessor's address bus outputs, or by using them during timing periods when the address bus outputs are isolated within the microprocessor. ing.

When writing data to a memory, consideration must be given to the fact that the data bus output and address bus output of the processor are at the signal display level at the same time.

An even bigger problem lies in the method of extracting data from the microprocessor at time n1 that is longer than the data width of its data bus output.

The present invention applies an address modification technique of index addressing to assemble nine data portions that protrude from the data bus output as part of an address signal within the range of margin bits in the address bus output of the processor. The true address signal and the data part are separated from the address bus in the memory, and the data part is combined with the data sent from the data bus separately, so that the address signal indicates the address signal. This solves the above-mentioned problem by writing them together at the same location.

The present invention has a configuration for this purpose, including a processor, the number of address digits is smaller than the number of digits output from the address bus of the processor by a fixed number A, and the number of digits of data at one address position is the number of digits output from the data bus of the processor. In a computer system (7-), the data of the certain number of digits A is stored in the range 1 of the certain number of digits A.
Memory write command index addressin 7″
'rD is set to a digit position that does not overlap with the memory address bus digit position of a register that can be handled by the bit line that corresponds to the digit position of the data of the specified number of people outputting the processor address bus. is used as a part of memory data input, and the writing process of data at one address position is completed by executing the memory write command once.

FIG. 1 is a conceptual explanatory diagram of rounding to facilitate understanding of the present invention. In FIG. 0, 1 is a 14-bit address prisoner,
2 is 10 bit data (d, D), 301
6-bit address bus and 4 8-bit data buses, 5 memory
Used as address, address and 6 write data.

Address bus 3 is a 14-bit address 1?4:
There is a margin of 2 bits to transfer I, and on the other hand, there is a shortage of 2 bits in the data bus number to transfer 10 bits of data (d, D) 2. Therefore, the address prisoner 1 The upper part of the data and the lower 2 bits of 10m are stored in the 16-bit register 7, and the data (d
L, D) Make the 2-bit data part (2) in 2 the lower part and the upper part as @o1, and create 9 data in register 8, and set these registers and the data in 8 as the address of the write command. Add index with modification and add 1
The 6-pit address (person, and) is synthesized into register 9.

Address (h e a) e of register 9 is sent as address (A, revised) 10 via address no (3). Address (A, (L) 10 is true on the address line on the memory side Address ■ and data (+1) K are separated, and data (d) is coupled to part of the data input of the memory. Data 0, on the other hand, is connected to register 1 in the usual way.
From 1 through the pass number, it is combined with the data in the memory as data 0.12. As described above, the address 5 and the data (d, D) 6 are correctly transferred to the memory.

FIG. 2 is a block diagram showing an embodiment of the invention.

In FIG. 2, A1 is a display memory, and CR7 stores character codes and attribute information to be displayed. Al1 is a memory chip address decoder, A @ A2 is a CRT display controller,
Rounding timing generation for CRT display control, parallel to serial conversion,
It has functions such as character pattern generation. A3 is a synchronization circuit, A4 is a CRT, 11A5 is an address decoder for memory translation, and Ml is an OR circuit.

Also, Dl is a-bit character data, DL is 8-bit attribution data, D3 is the memory chip address, D4 is the address in the memory chip, and D51D6 is the CR.
These are address lines and data lines for reading out the operating conditions of the T display controller A2. DB is an 8-bit chip fi /(x, AB is 16
This is the bit address bus.

FIG. 3 is a diagram showing the allocation of the 16-bit Φ address bus. D3. It shows the bit position of D4. The lower two bits of data D2 are taken out from the address bus AB and added to the data input of the memory IJAl together with the data D1 from the data bus DB. The upper 14 bits D3 and D4 of the address bus are sent to the decoder A.
5, becomes an address selection signal for the memory A1 via A l'.

Next, an example of a zologram used in the write control of the present invention is shown below.

■ LD R1, ATRIB ■ LD The instruction to load the display memory address, ■The instruction to load the character code for sub-display from the DCHR address to the register RO, ■ is the original data (RO) (R1+XO)
This is an instruction to write to an address, but according to the method of the present invention, data [to.

This is an instruction to execute the process of writing R11 to the XO address.

Applying the nine programs mentioned above to the example shown in Figure 2, we get
Data [XO] is address (D3*D4), data) [R
O) corresponds to Dl, and data [R1] corresponds to 02.

The present invention has been described in detail above, and by applying the present invention, the number of memory convolutions is reduced, so that the processing speed is increased and the memory control circuit can be saved. Furthermore, the effect of reducing the number of zologram steps is significant.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a configuration diagram of an address bus output used in the embodiment shown in FIG. In the figure, l is the address to be transferred, 2 is the data to be transferred 5.3
line address bus, number is the data bus, 5 is the transferred address, 6 is the transferred data, 8 is the register used for index finger addressing, 10 is the address on the address bus, 11 is the address data register, 1
2 represents data on the data bus. Patent applicant Fujitsu Limited

Claims (1)

[Claims] a processor, the number of address digits is a certain number of digits less than the number of digits output from the address bus of the processor, and the number of digits of data at one address position is less than the number of digits output from the data bus of the processor; In a computer system having a large amount of memory within the range, the data of the certain number of digits A is stored as an index of a memory write command.
The addressing function is set to a digit position that does not overlap with the memory address digit position of the register that can be handled, and the bit line corresponding to the digit position of the data of the certain number of digits A being outputted from the Zorocera T address bus is connected to the memory address. - A data write control method, which is used as part of data input, and is characterized in that the write process of data at one address position is completed by one execution of the memory write instruction.